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Z80 Second Processor Functional Block Diagram

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Summary of Contents for Z80 Second Processor

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Page 3: ...Z80 SECOND PROCESSSOR SERVICE MANUAL Part No 0409 015 Issue 2 August 1984 ...

Page 4: ...ual can be obtained upon request from Acorn Computers Technical Enquiries Acorn Computers welcome comments and suggestions relating to the product and this manual All correspondence should be addressed to Technical Enquiries Acorn Computers Limited Newmarket Road Cambridge CB5 8PD All maintenance and service on the product must be carried out by Acorn Computers authorised dealers Acorn Computers c...

Page 5: ...7 5 8 DRAM R e f r e s h 9 5 9 Desynchronising Logic 10 5 10 The Tube 11 6 Fault Finding on the Z80 Second Processor 17 6 1 General 17 6 2 Fault Conditions 17 6 3 Circuit Checks 19 Appendix Diagnostic Flowcharts 25 Z80 Second Processor Block Diagram 37 Circuit Diagram 39 Z80 PCB Component Layout 41 Silk Screen 43 Power Supply Unit Circuit Diagram 45 Z80 Second Processor General Assembly 47 Parts L...

Page 6: ...ket outlet available is not suitable for the plug supplied the plug should be cut off and the appropriate plug fitted and wired as previously noted The moulded plug which was cut off must be disposed of as it would be a potential shock hazard if it were to be plugged in with the cut off end of the mains cord exposed The moulded plug must be used with the fuse and fuse carrier firmly in place The f...

Page 7: ...m which was designed by Acorn Computers Ltd of Cambridge England The information contained in this manual is aimed at Acorn dealers and service engineers who will be servicing the Z80 second processor on behalf of Acorn Computers Ltd Z80 is a trademark of Zilog Inc CP M is a registered trademark of Digital Research Inc The Tube is a trademark of Acorn Computers Limited ...

Page 8: ...be packed in plastic bags and laid flat The Z80 Second Processor User Guide and accompanying literature is supplied packed separately A mains power switch is located at the rear of the second processor A 250mA type T slow blow fuse is located at the rear of the second processor Before removing this fuse the second processor must be disconnected from the mains supply Access to the fuse may be gaine...

Page 9: ...U 64K of read write Random Access Memory 4K Read Only Memory shadow ROM providing a boot function on power up and to handle Non Maskable Interrupts NMI from the Host processor via the Tube The Tube a fast asynchronous communication path connecting the second processor to the I O processor BBC Microcomputer A mains operated integral power supply comprising a mains transformer and power supply board...

Page 10: ...two rubber feet The assembly diagram is given in the Appendix The lid can now be removed revealing the transformer and power supply board held in place by six screws and the Z80 PCB It is recommended that the transformer and power supply board are not removed unless absolutely necessary To remove the Z80 PCB from the case pu11 off the two fast on tabs which connect the power supply brown 5v and bl...

Page 11: ...then the D output is available for use as an inverted clock by the DRAM control and the desync logic 5 3 ROM Latch The Z80 second processor features a shadow ROM to boot the system upon power up and also to ensure proper handling of NMI interrupts from the host processor via The Tube The ROM is enabled at the proper times by the latch IC15A 1 After power up the reset signal from IC24F to the Z80 i...

Page 12: ... the NAND gate IC21C a low going pulse of 1 clock cycle is fed to the WAIT input of the Z80 see timing diagram above The Wait generator requires a further two clock cycles after the end of the lengthened memory cycle to clear itself The Z80 samples the WAIT input on the falling edge of 0 t1 TP7 a11ows observation of the WAIT signal 5 5 Reset The Z80 second processor may be reset at any time by the...

Page 13: ...ss for the interrupt vector of 0FFFEH 5 7 DRAM Control 5 7 1 Read Write Cycles a RAS Whenever a memory cycle occurs the preset signal on the D latch IC17B is removed by the MREQ signal from the Z80 On the next rising edge of the system clock the D latch output goes low giving the CHOP signal During memory read or write cycles the fa11ing edge of CHOP produces the row address RAS signal TP8 via IC2...

Page 14: ...Fetch differently to other memory read cycles in that the MREQ signal is active for only 1 5 clock cycles instead of 2 In order to allow sufficient access time for the DRAMS in this abbreviated cycle the Instruction Fetch signal Ml is used to generate the RAS and CAS signals a half cycle earlier The OR gate IC23A allows the clock signal through to the D latch IC18A only when M1 is active The outpu...

Page 15: ... Z80 CPU performs a Refresh cycle for the DRAMS in the period while the instruction is being decoded A seven bit refresh address is output onto the address bus A0 to A6 A7 0 for approx 2 clock cycles and the MREQ signal goes low The RFSH signal from the Z80 is not used and no other ...

Page 16: ...ssor when the PCS and HCS signals occur simultaneously When this happens a low signal from IC29B pin 6 appears at IC30A pin 2 Q on IC30A goes high and via IC29A maintains a logic 1 signal upon pin 12 of IC30B thus by the end of one clock cycle a high is sent from pin 9 of IC30B to disable PCS Simultaneously a WAIT signal is generated for the second processor via IC19A B As soon as HCS TP6 is remov...

Page 17: ...4 write only 8 bit registers The Z80 accesses these registers via its I O structure Fig 5 Tube concept 5 10 1 Tube Registers Each register has its own status byte with a separate I O address containing Register Fu11 and Data Available flags The status byte for Register 1 contains additional control bits that may be set by the Host computer to enable interrupts or to reset the Z80 These control bit...

Page 18: ...Fig 6 Schematic diagram of Tube registers ...

Page 19: ...Address Write 000 Status Flags 001 Register 1 1 byte write only 010 011 Register 2 1 byte write only 100 101 Register 3 2 byte FIFO write only 110 111 Register 4 1 byte write only Table 2 Parasite system registers Address Read 000 Status flags and Register 1 flags Al Fl P V M J I Q 001 Register 1 1 byte read only 010 Register 2 flags 011 Register 2 1 byte read only 100 Register 3 flags 101 Registe...

Page 20: ...rom the Parasite Z80 to the Post but a simple latch from Post to the Parasite The Tube produces maskable and non maskable interrupts to the Parasite see sections 5 6 and 5 3 and a reset signal section 5 5 The Z80 IORQ and M1 signals are decoded to detect an I O cycle by the OR gate IC22A which provides the signal which via the De sync circuit initiates the chip select PCS to the Tube The Tube thus...

Page 21: ...h level signifies valid address bus PR W Post read write line determines whether read or write register is selected on address specified by PAO 2 and direction of data flow on PD0 7 PNRDS Parasite read strobe active low PNWDS Parasite write strobe active low Interrupt lines PRST Host reset RST initialises Tube to known state and generates PRST PRST Reset RST line to parasite processor PNM1 Non mas...

Page 22: ...PCS direction is given by PNRDS or PNWDS and timing by PCS MIN MAX 1 R W SET UP TO 02 35ns 2 TIMING STROBE PULSE WIDTH 110ns 3 ADDRESS SET UP TIME 35ns 4 ADDRESS CHIP SELECT POLD TIMES 10ns 5 DATA OUT DELAY TIME 70ns 6 DATA OUT POLD TIME 10ns 7 DATA IN SET UP TIME 5Ons 8 DATA 1N HOLD T1ME 20ns 9 R W POLD T1ME 10ns 10 CYCLE TIME 250ns 11 CS SET UP T1ME 20ns ...

Page 23: ...used in interrupt handling TP4 MREQ goes low to indicate memory addressing TP5 PCS indicates successful parasite chip select to Tube via de sync logic circuit TP6 HCS indicates Post chip select to tube TP7 WAIT Occurs during reads from the ROM and as result of simultaneous HCS PCS event Enables refresh cycles TP8 RAS Row Address Signal used in ALL memory addressing both for accessing and refreshin...

Page 24: ...ing intermittently Check by first replacing IC1 1C2 and IC3 in turn then check operation once warm use a freezer spray to locate temperature sensitive components Flashing Cursor in the top left corner of an otherwise blank screen Total Failure This is the most usual result of plugging in a broken Z80 second processor as the majority of faults manifest themselves in this way Normal Operation until ...

Page 25: ...d CPOP signals respectively independently of each other but both are required to be operating for full RAS ability RAS may therefore be appearing due to only one of the two Dtypes working so check that pins 1 and 2 of both IC20A and IC21A are operating If not check the operation of the Dtypes according to inputs RAS wi11 fail if the CPU is not operating as it requires Ml and MREQ as we11 as the cl...

Page 26: ...and replace if necessary The output of IC14 appears at pin 10 of IC19C from here on the reset function is common to both power up and BREAK as follows The reset signal from IC19C is inverted by IC24F and appears at pin 26 of IC2 CPU reset and also at pin 3 of IC 15A ROM latch so that if 1C15A is functioning correctly a reset should cause a low going pulse to appear at IC2 pin 26 reset active low f...

Page 27: ...pears at pin 17 of IC2 NMI the address lines should be seen to address 066H instruction fetch This should decode through IC26 27 to give the NMISERV signal Failure of this circuit wi11 prevent disk access If this occurs check 0D clock circuit that NMI from IC2 pin 17 appears at pin 5 of IC21B and that NMISERV from pin 9 of IC27 appears at pin 4 of IC15A and IC21D pin 12 Check for broken tracks and...

Page 28: ...low fuse FS1 Supply rail cut off is therefore achieved if the voltage reaches approximately 6 1V If fuse FS1 is blown it could be due to either overvoltage or overcurrent and there is likely to be either a short circuit somewhere or the power supply board is faulty it is supplying too high a voltage Disconnect the two power supply leads brown and black from the second processor PCB and connect a 1...

Page 29: ... CAUSE INJURY 6 3 10 Checking the Tube power supplies The Tube IC1 is powered both from the BBC Microcomputer and from the second processor If either of these supplies fails then the second processor wi11 not work With the second processor switched off ON OFF switch down switch on the BBC Microcomputer ON OFF switch up Check that there is a potential of approx 5V between pin 4 ve and pins 1 and 5 ...

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Page 31: ...Diagnostic Flowcharts Note The letters in circles refer to the relevant flowcharts which follow Master Flowchart ...

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Page 41: ...Power Supply 3 5 ...

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Page 43: ...Z80 Second Processor Functional Block Diagram ...

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Page 45: ...Z80 second Processor PCB Circuit Diag ...

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Page 49: ...Z80 PCB Silk Screen 43 ...

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Page 51: ...Power Supply Circuit Diagram ...

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Page 53: ...Z80 Second Processor General Assembly 47 ...

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Page 55: ...o6 x 13mm 3 BLACK 26 890 000 STICK ON FOOT 4 Z80 PCB Assembly SEE PAGE 41 4 502 103 RESISTOR 10K 1 4W 5 1 R7 5 502 821 RESISTOR 820R 1 4W 5 2 R3 4 6 502 220 RESISTOR 22R 1 4W 5 1 R8 7 502 221 RESISTOR 220R 1 4W 5 2 R6 9 8 502 122 RESISTOR 1K2 1 4W 5 1 R5 9 502 120 RESISTOR 12R 1W 10 1 R2 10 502 391 RESISTOR 390R 1 4W 5 1 R11 11 502 102 RES1STOR 1K 1 4W 5 1 R1 12 628 101 CAPACITOR 100nF CERAMIC 1 C...

Page 56: ...2 INTEGRATED CIRCUIT 74LS32 3 IC22 23 29 39 741 004 INTEGRATED CIRCUIT 74S04 1 IC24 40 742 004 INTEGRATED CIRCUIT 74LS04 1 IC25 41 742 260 INTEGRATED CIRCUIT 74LS260 1 IC26 42 742 133 INTEGRATED CIRCUIT 74LS133 1 IC27 43 800 037 S H E CONNECTOR 1 PL1 PALF 45 791 000 THYRISTOR C122F 1 TH1 46 783 906 TRANSISTOR 2N3906 1 Q1 47 880 049 INSULATOR 1 FOR 1TEM 45 48 820 120 CRYSTAL 12MPz 1 X1 50 815 007 F...

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