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Manual PCIe-DIO-144
Chapter 1: Introduction
The PCIe-DIO-144 series are x1 lane PCI Express (PCIe) boards with 144 digital I/O
lines designed for use in a variety of Digital I/O (DIO) applications. They use the high
speed PCIe bus to transfer digital data to and from the board. The FPGA based DIO
emulates 8255 compatible chips in mode 0, making it easy to program. This also allows
for simple migration from older ACCES’ PCI-based DIO boards. Lastly, the x1 lane PCIe
connector is very flexible and can be inserted into any x1, x4, x8, x16, or x32 PCIe slot.
Features
• 144 high-current DIO lines
• IRQ generation from DIO Bit C3 on each connector
• DIO lines buffered
• Five 50 pin male headers on side of card, one DB37F on mounting bracket
• Four and eight bit ports independently selectable for inputs or outputs
• Per port jumper selectable 10k ohm Pull-up/Pull-down resistors on DIO lines
• Global jumper selectable VCCIO (5V, 3.3V, 2.5V, 1.8V)
• VCCIO voltage available to the user via 0.5A resettable fuse
• Compatible with industry standard I/O racks like Grayhill, Opto 22, Western Reserve
Controls, etc.
Applications
• Automatic Test Systems
• Security Systems, Energy Management
• Robotics
• Relay Monitoring and Control
• Parallel Data Transfer to PC
• Sensing switch closures or TTL, DTL, CMOS Logic
• Driving Indicator Lights or Recorders
Functional Description
Buffers
Each I/O line is buffered and capable of sourcing or sinking 32mA when VCCIO is
configured for 5V. The board contains FPGA circuitry that emulates type 8255 mode 0
Programmable Peripheral Interface (GROUP) to provide a computer interface to digital
I/O lines. Each group supports two 8-bit ports (A, B) and two 4-bit ports (CHi, CLo). Each
port can be configured to function as either input or output latches. The I/O line buffers
are configured automatically by hardware logic for input or output according to the
GROUP Control Register direction software assignment. All DIO lines can be tristated as
well using the corresponding software command.
