Manual 104-QUAD-8
16
Writing to the IDR (Index Control Register):
Bit 0:
Set high to enable index.
Bit 1:
Set high for a positive index polarity.
Set low for a negative index polarity.
Bit 2:
Set low.
Bits 3 & 4:
Not used.
Bits 5 & 6:
Set high.
Bit 7:
Set high to program both counters simultaneously.
Working with Interrupts:
Reading the Interrupt Status Register (10h)
When an interrupt occurs read from address 10h to determine which channel was the source.
Bit 0-7:
The Least Significant Bit will correspond to the first channel.
High = true
Writing to the Channel Operation Register (11h)
Any write to this address will clear any pending interrupts.
A read from this address will return it’s contents.
Bit 0: Set high to reset all Counters.
Set low to enable all Counters.
Bit 1: Reserved.
Bit 2: Set low to disable the interrupt function.
Set high to enable the interrupt function.
Bits 3-7: Reserved.
