Manual 104-QUAD-8
17
Writing to the Index / Interrupt Register (12h)
This register is used to Preset Counter via the LCNTR input pin when a channel index
occurs as described in
Writing to the IOR
and
Writing to the IDR
.
Additionally it is used to generate interrupts whenever FLG1 on a channel is active as
described in
Writing to the IOR
and
Writing to the Channel Operation Register.
Each bit of this register enables / disables a corresponding channel.
A read from this address will return it’s contents.
Bit 0: Set high to enable Channel 1
Bit 1: Set high to enable Channel 2
Bit 2: Set high to enable Channel 3
Bit 3: Set high to enable Channel 4
Bit 4: Set high to enable Channel 5
Bit 5: Set high to enable Channel 6
Bit 6: Set high to enable Channel 7
Bit 7: Set high to enable Channel 8
Reading Index Input Levels (16h)
Bit 0 through 7 correspond to channels 1 through 8.
Logic 0 = Index Input low (false).
Logic 1 = Index Input high (true).
*If your encoder does not have an Index signal, the Index Positive Input pin needs to be
grounded or the corresponding channel bit will return a logic 1 level.
Reading Differential Encoder Cable Status (17h)
Bit 0 through 7 correspond to channels 1 through 8.
To enable any channel write a 0 to the corresponding bit.
When enabled, Logic 0 = cable fault (not connected or loose wires).
Logic 1 = cable connection good or cable fault disabled (default).
Bits 0 through 7 will always read a high when disabled.
Reading the CPLD Revision Register (18h)
To determine the CPLD Revision read from address 18h
Old card revisions B10 and earlier will read FF
Revision C1 cards will read 00
Revision C2 cards will read 01