Manual PCIe-DIO-24HS PCI Express Digital I/O Card
6
This board has two methods for generating an interrupt. The first is using bit 3 of Port C (C3
IRQ). When this method is enabled, a rising signal edge detected on bit 3 of Port C will
generate an interrupt. The second method uses COS detection hardware to produce an
interrupt ('S' model only). When a Port has COS enabled, any changes of the Port's bits (low-
to-high or high-to-low) will cause an interrupt. Refer to Chapter 5: Programming for enabling,
disabling, and clearing the interrupts.
Each DIO line is buffered and capable of sourcing 32mA or sinking 64mA. The VCCIO level is
5V or can be configured as 3.3V.
By default, the DIO lines are pulled up with 10kΩ resistor networks to VCCIO. DIO lines can
also be configured as pulled down by moving a jumper.
DIO wiring connections are via the 50-pin header on the mounting bracket of the board. This
provides compatibility with OPTO-22, Gordos, Potter & Brumfield, and other module mounting
racks. Every second conductor of the ribbon cable is grounded to minimize crosstalk between
signals in the cables. VCCIO is available on each I/O connector (pin 49) for external use, see
page 10.
Figure 1-1:
Block Diagram
