Manual PCI-DIO-48JP/JPS
13
Chapter 6: Programming
These cards are I/O-mapped devices that are easily configured from any language and any language can
easily perform digital I/O through the card's ports. This is especially true if the form of the data is byte or
word wide. All references to the I/O ports would be in absolute port addressing. However, a table could be
used to convert the byte or word data ports to a logical reference.
DEVELOPING YOUR APPLICATION SOFTWARE
If you wish to gain a better understanding of the programs on diskette, then the information in the following
paragraphs will be of interest to you. Refer to the data sheets and 8255-5 specification in Appendix A.
A total of 16 register locations are used by these. The PPIs are addressed consecutively with Address bits
A3 through A0 as follows:
Address Port
Assignment
Operation
Base Address
Base A1
Base A2
Base A3
Base A4
Base A5
Base A6
Base A7
Base A8
Base A9
Base AB
Base AF
Port A Group 0
Port B Group 0
Port C Group 0
Control Group 0
Port A Group 1
Port B Group 1
Port C Group 1
Control Group 1
Enable/Disable Buffer, Grp 0
Enable/Disable Buffer, Grp 1
Enable Chg-of-St. Interrupt
Clear Chg-of-St. Interrupt
Read/Write
Read/Write
Read Write
Write Only
Read/Write
Read/Write
Read/Write
Write Only
Write Only
Write Only
Write Only
Write Only
Table 6-1: Address Assignment Table
These cards use two type 8255-5 PPIs to provide a total of 48 bits input/output capability. The cards are
designed to use each of these PPI's in Mode 0 wherein:
a. There are two 8-bit groups (A and B) and two 4-bit groups (C Hi and C Lo).
b. Any group can be configured as an input or an output.
c. Outputs are latched.
d. Inputs are not latched.
Each PPI contains a Control Register. This write-only, 8-bit register is used to set the mode and direction of
the ports. At Power-Up or Reset, all I/O lines are set as inputs. Each PPI should be configured during
initialization by writing to the Control Registers even if the groups are only going to be used as inputs.
Output buffers are automatically set by hardware according to the Control Register states. Note that Control
Registers are located at base a3 and base a7. Bit assignments in each of these Control
Registers are as follows:
