ACCES I/O Products, Inc.
MADE IN THE USA
mPCIe- and M.2-AIO16-16F Family Manual
10
Rev B6e
Write IRQ Enable bits SET to enable corresponding IRQ sources.
DIO Data, 44 of 32-bit Memory BAR[1]Read/Write 32-bits only
bit D31 through D2
D1
D0
Name UNUSED
DIO1
DIO0
Read DIO Data to read the digital input pins or to readback the last commanded digital output state.
Write to DIO Data to configure the digital pin(s)’ high/low state for those bits in I/O Groups configured as
Outputs. SET bits will output high voltage, CLEAR bits will output GND.
Refer to DIO Control (+48) for how to configure the input vs output direction of each I/O Group.
DIO Control, 48 of 32-bit Memory BAR[1]Read/Write 32-bits only
bit
D31…D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15 … D2
D1
D0
Name UNUSED enWDG edgeEXT1 enEXT1 edgeEXT0 enEXT0 edgeLDAC enLDAC edgeSTART
enSTART edgeTRIG
enTRIG
UNUSED
I/O Group 1
I/O Group 0
Write DIO Control to enable Digital Secondary Functions, and to control the input vs output direction of each Digital I/O Group.
enWDG:
SET enWDT to enable the “WDT Output Status” Digital Output Secondary Function on DIO 1. DIO 1 (I/O Group
1) becomes an output and indicates the state of
the Watchdog Feature.
enEXT
n
:
SET enEXT0 or enEXT1 to enable the corresponding
“External IRQ” Digital Input Secondary Function on DIO
0/1 so the selected edge on the input will
(optionally) generate IRQs.
enLDAC:
SET enLD
AC to enable the “External LDAC” Digital Input Secondary Function on DIO
1 so the selected edge will cause the DACs to update and optionally
generate an IRQ.
enSTART:
SET enSTART to enable the “ADC Start Conversion” Digital Input Secondary Function on DIO
0 so the selected edge will cause an ADC Start Event and optionally
generate an IRQ.
enTRIG:
SET enTRIG to enable the “ADC Trigger”
Digital Input Secondary Function on DIO 0 so the selected edge will trigger timed ADC conversions and optionally
generate an
IRQ. Consult the “Software Tips” section for details on using ADC Trigger.
Each Digital Input Secondary function has a configurable active edge, rising or falling. SET the corresponding edge
XXX
bit to select rising edge, CLEAR the bit for falling edge.
I/O Group1:0
SET each bit to configure the digital I/O bit in the associated I/O Group for use as digital outputs. CLEAR a
bit to configure the I/O Group for use as inputs.
(D0 is I/O Group 0 which controls the output vs input direction of DIO 0; D1 is I/O Group 1 which controls the direction of DIO1)
Watchdog Control, 4C of 64-bit Memory BAR[2+3] Read/Write 32-bits only
bit D31 D30 D29 D28 D27 D26 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Name Watchdog Timeout
Write the number of Ticks (which occur at the ADC Base Clock Rate (+C)) before the Watchdog should timeout (“Bark”); e.g., fo
r a one-second timeout period write the value read from
+C to +4C.
When the Watchdog Barks the board is RESET as if just powered on (or as if a 1 is written to the Resets and Power (+0) register) with the following exceptions:
If enWDG,
the “WDT Output Status” DIO Secondary
Output Function is enabled then DIO 1 remains an output and asserts 0.
Bit D31 of the IRQ Enable/Clear and Status
(+40) “WDG” is latched SET to indicate that the Watchdog timed out.
Write 0 to the Watchdog Timeout (+4C) register to disable the Watchdog Feature.
