ACCES I/O Products, Inc.
MADE IN THE USA
mPCIe- and M.2-AIO16-16F Family Manual
8
Rev B7a
ADC FIFO Almost Full IRQ Threshold, 20 of 32-bit Memory BAR[1]Read/Write 32-bits only
bit D31 through D12
D11 through D0
Name UNUSED
FAF
FAF:
Write any 12-bit value (0..4095) to set the amount of entries in the ADC FIFO allowed to accumulate before a FIFO Almost Full IRQ is fired.
In Software ADC Start mode (ADC Rate Divisor (+10) cleared to zero) the FIFO is 32-bits wide, able to hold up to 4095 conversion results (+statuses).
In all other ADC Start Modes the ADC FIFO is 64-bits wide, holds two ADC Conversions (+statuses) per FIFO entry and the FIFO thus holds 8190 conversion/status pairs. Refer to
the ADC FIFO (+30) register description for more details.
ADC FIFO Count, 28 of 32-bit Memory BAR[1]Read-Only 32-bits only
bit D31 through D12
D11 through D0
Name UNUSED
FIFO Count
FIFO Count:
Read FIFO Count to determine how many entries the ADC FIFO contains.
In Software ADC Start Mode (ADC Rate Divisor (+10) cleared to zero) the FIFO Count determines how many ADC Conversions (+statuses) are held in the FIFO. Read the ADC FIFO
this many times to gather the acquired ADC Data.
In all other modes the FIFO Count reports the number of
pairs
of ADC Conversions are available in the FIFO. Were you to read the data from the ADC FIFO (+30) you would read
two 32-bit values per FIFO Count to gather the acquired data. However, in these modes it is generally best to let DMA transfer the FIFO data, which is performed at the native
64-bit FIFO width.
ADC FIFO Data, 30 of 32-bit Memory BAR[1]Read-Only 32-bits only
bit D31
D30
D29 D28 D27 D26 D25
D24 D23 D22 through D20 D19 D18 through D16 D15 through D0
Name INVALID=1
RUNNING UNUSED
0 (“VALID”)
RSV
DIO1 DIO0 RSV
RSV
TEMP MUX SEQ Channel2:0
Diff Gain2:0
ADC Counts (Two’s complement)
ADC FIFO Data: Read the RAW-format ADC Conversion results (in twos-complement 16-bit form) and the associated status word.
INVALID:
If INVALID is SET then all other bits are undefined, and the entry should be discarded. This can occur if you read from the ADC FIFO while the ADC FIFO Count
(+28) is zero.
RUNNING:
SET indicates the ADC Sequencer is operating, taking either periodic (timer-driven) conversions or via the external ADC Start secondary digital function.
DIO1:0:
These bits indicate the state of the corresponding digital I/O pin at the time the paired ADC Conversion was sampled.
TEMP:
If TEMP is SET the ADC Counts are acquired from the ADAS3022’s onboard temperature sensor rather than from an analog input ch
annel. Refer to ADC Control
(+38) for more information about acquiring the temperature data.
MUX:
If MUX is SET the ADC Counts are acquired from the ADAS3022’s Auxiliary Mux inputs rather than from the normal Analog Input C
hannels. Note, the mPCIe-
AIO16-16F does not have anything usefully connected to the Aux Mux inputs and you should not bother acquiring data from them.
SEQ:
The SEQ bit indicates which ADC the data is from, and can be thought of as Channel:3. That is, if SEQ is set add +8 to the channel reported by the Channel2:0
bits.
Channel2:0:
The 3 Channel bits indicate from which Analog Input the paired ADC Counts were sampled. Refer to ADC Control (+38) for important information about the
Channel bits re Differential operation.
Diff:
SET indicates the paired ADC Counts were sampled in Differential mode. Refer to ADC Control (+38) for important information about the Channel bits re
Differential operation.
Gain2:0:
The 3 Gain bits indicate at what gain code the paired ADC Counts were sampled. Refer to the gain code table in ADC Advanced Sequencer Gain Control (+18)
for how to interpret the Gain bits.
