Abov MC96F6332D, User Manual

Page: 208 / 327

MC96F6432
208 June 22, 2018 Ver. 2.9
Figure 11.65 USI0 SPI Clock Formats when CPHA0=1
When CPHA0=1, the slave begins to drive its MISO0 output when SS0 goes active low, but the data is not
defined until the first SCK0 edge. The first SCK0 edge shifts the first bit of data from the shifter onto the MOSI0
output of the master and the MISO0 output of the slave. The next SCK0 edge causes both the master and slave
to sample the data bit value on their MISO0 and MOSI0 inputs, respectively. At the third SCK0 edge, the USI0
shifts the second data bit value out to the MOSI0 and MISO0 output of the master and slave respectively. When
CPHA0
=1, the slave’s SS0 input is not required to go to its inactive high level between transfers.
Because the SPI logic reuses the USI0 resources, SPI mode of operation is similar to that of synchronous or
asynchronous operation. An SPI transfer is initiated by checking for the USI0 Data Register Empty flag (DRE0=1)
and then writing a byte of data to the USI0DR Register. In master mode of operation, even if transmission is not
enabled (TXE0=0), writing data to the USI0DR register is necessary because the clock SCK0 is generated from
transmitter block.
SCK0
(CPOL0=1)
MISO0
MOSI0
SCK0
(CPOL0=0)
/SS0 OUT
(MASTER)
BIT7
BIT0
/SS0 IN
(SLAVE)
BIT6
BIT1
…
…
BIT2
BIT5 BIT0
BIT7 BIT1
BIT6
SAMPLE
MSB First
LSB First