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Abov A96G140 User Manual Download Page 223

A96G140/A96G148/A96A148 User’s manual

   

 

18. Reset 

 

223 

 

 
 

Figure 116. Fast VDD Rising Time 

 

 

Figure 117. Internal RESET Release Timing On Power-Up 

 

 

VDD 

nPOR 

(Internal Signal) 

Internal RESETB 

Oscillation 

BIT Starts 

BIT Overflows 

Slow VDD Rising Time, min. 0.05V/ms 

V

POR

=1.32V (Typ) 

VDD 

nPOR 

(Internal Signal) 

Internal RESETB 

Oscillation 

BIT Starts 

BIT Overflows 

Fast VDD Rising Time, max. 50.0V/ms 

Summary of Contents for A96G140

Page 1: ...incorporates followings to offer highly flexible and cost effective solutions 64Kbytes of FLASH 256bytes of IRAM 2304bytes of XRAM general purpose I O basic interval timer watchdog timer 8 16 bit timer counter 16 bit PPG output 8 bit PWM output 16 bit PWM output watch timer buzzer driving port USI 12 bit A D converter on chip POR LVR LVI on chip oscillator and clock circuitry As a field proven bes...

Page 2: ...s 47 6 1 Port register 47 6 1 1 Data register Px 47 6 1 2 Direction register PxIO 47 6 1 3 Pull up register selection register PxPU 47 6 1 4 Open drain Selection Register PxOD 47 6 1 5 De bounce Enable Register PxDB 47 6 1 6 Port Function Selection Register PxFSR 47 6 1 7 Register Map 48 6 2 P0 port 49 6 2 1 P0 port description 49 6 2 2 Register description for P0 49 6 3 P1 port 52 6 3 1 P1 port d...

Page 3: ... 6 Interrupt register description 75 8 Clock generator 82 8 1 Clock generator block diagram 82 8 2 Register map 83 8 3 Register description 83 9 Basic interval timer 86 9 1 BIT block diagram 86 9 2 BIT register map 86 9 3 BIT register description 87 10 Watchdog timer 88 10 1 WDT interrupt timing waveform 88 10 2 WDT block diagram 89 10 3 Register map 89 10 4 Register description 89 11 Watch timer ...

Page 4: ...138 12 6 Timer 5 141 12 6 1 16 bit timer counter mode 141 12 6 2 16 bit capture mode 143 12 6 3 16 bit PPG mode 144 12 6 4 16 bit timer 5 block diagram 147 12 6 5 Register map 147 12 6 6 Register description 147 13 Buzzer driver 150 13 1 Buzzer driver block diagram 150 13 2 Register map 150 13 3 Register description 151 14 12 bit ADC 152 14 1 Conversion timing 152 14 2 Block diagram 152 14 3 ADC o...

Page 5: ...ceiver 177 15 19 3USIn I2C slave transmitter 178 15 19 4USIn I2C slave receiver 179 15 20 USIn I2C block diagram 181 15 21 Register map 181 15 22 USIn register description 182 15 23 Baud rate settings example 190 16 USART2 193 16 1 Block diagram 194 16 2 Clock generation 195 16 3 External clock XCK 196 16 4 Synchronous mode operation 196 16 5 Data format 197 16 6 Parity bit 198 16 7 USART2 transmi...

Page 6: ...erial in system program mode 240 19 3 1 Flash operation 240 19 4 Mode entrance method of ISP mode 246 19 4 1 Mode entrance method for ISP 246 19 5 Security 247 19 6 Configure option 247 20 Development tools 250 20 1 Compiler 250 20 2 Core and debug tool information 251 20 2 1 Feature of 94 96 97 series core 251 20 2 2 OCD type of 94 96 97 series core 253 20 2 3 Interrupt priority of 94 96 97 serie...

Page 7: ...se Timing Diagram 73 Figure 23 Correspondence between Vector Table Address and the Entry Address of ISR 73 Figure 24 Saving Restore Process Diagram and Sample Source 73 Figure 25 Timing Chart of Interrupt Acceptance and Interrupt Return Instruction 74 Figure 26 Clock Generator Block Diagram 83 Figure 27 Basic Interval Timer Block Diagram 86 Figure 28 Watch Dog Timer Interrupt Timing Waveform 88 Fi...

Page 8: ...Timer Counter Mode of Timer 5 142 Figure 71 16 bit Timer Counter Mode Operation Example 142 Figure 72 16 bit Capture Mode of Timer 5 143 Figure 73 16 bit Capture Mode Operation Example 144 Figure 74 Express Timer Overflow in Capture Mode 144 Figure 75 16 bit PPG Mode of Timer 5 145 Figure 76 16 bit PPG Mode Operation Example 146 Figure 77 16 bit Timer 5 Block Diagram 147 Figure 78 Buzzer Driver Bl...

Page 9: ...RESET 226 Figure 121 Oscillator generating waveform example 226 Figure 122 Block Diagram of LVR 227 Figure 123 Internal Reset at Power Fail Situation 227 Figure 124 Configuration Timing When LVR RESET 228 Figure 125 LVI Block Diagram 228 Figure 126 Read Device Internal Checksum Full Size 237 Figure 127 Read Device Internal Checksum User Define Size 238 Figure 128 Flash Memory Map 240 Figure 129 Ad...

Page 10: ...List of figures A96G140 A96G148 A96A148 User s manual 10 ...

Page 11: ...Register Map 138 Table 25 TIMER 5 Operating Modes 141 Table 26 TIMER 5 Register Map 147 Table 27 Buzzer Frequency at 8MHz 150 Table 28 Buzzer Driver Register Map 151 Table 29 ADC Register Map 155 Table 30 Equations for Calculating USIn Baud Rate Register Setting 160 Table 31 CPOLn Functionality 168 Table 32 USI Register Map 181 Table 33 Example1 of USI0BD and USI1BDSettings for Commonly Used Oscil...

Page 12: ...terfaces by Series 251 Table 52 Feature Comparison Chart By Series and Core 252 Table 53 OCD Type of Each Series 253 Table 54 Comparison of OCD 1 and OCD 2 253 Table 55 Interrupt Priorities in Groups and Levels 254 Table 56 Debug Feature by Series 256 Table 57 OCD 1 and OCD 2 Pin Description 257 Table 58 OCD Features 258 Table 59 Pins for Flash Programming 266 Table 60 Instruction Table 270 ...

Page 13: ...cription Core CPU 8 bit CISC core M8051 2 clocks per cycle Interrupt Up to 23 peripheral interrupts supported EINT0 to 7 EINT8 EINT10 EINT11 EINT12 5 Timer 0 1 2 3 4 5 6 WDT 1 BIT 1 WT 1 USART Rx Tx 2 USI 2 ch Rx Tx I2C 6 ADC 1 LVI 1 Memory ROM FLASH capacity 64 32 Kbytes FLASH with self read and write capability In system programming ISP Endurance 30 000times IRAM 256Bytes XRAM 2304Bytes Programm...

Page 14: ...x 5 ch T1 T2 T3 T4 T5 Communication function USART2 8 bit USART x 1 ch or 8 bit SPI x 1 ch Receiver timer out RTO 0 error baud rate USI0 1 USART SPI I2C 8 bit USART x 2 ch or 8 bit SPI x 2 ch or I2C x 2 ch 12 bit A D converter 16 input channels Oscillator type 4MHz to 12MHz crystal or ceramic for main clock 32 768kHz Crystal for sub clock Internal RC oscillator HSI 32MHz 1 5 TA 0 50 C HSI 32MHz 2 ...

Page 15: ...s manual 1 Description 15 Table 1 A96G140 A96G148 A96A148 Device Features and Peripheral Counts continued Peripherals Description Package Pb free packages 48 LQFP 7x7 mm 48 QFN 6x6 mm 44 MQFP 10x10 mm 32 LQFP 32 SOP 28 SOP 28 TSSOP ...

Page 16: ...cator Power down mode Clock generator 32MHz Internal RC OSC 128kHz Internal RC OSC 12MHz Crystal OSC 32 768kHz Crystal OSC Buzzer 1 channel 8 bit UART 3 channels 8 bit SPI 3 channels 8 bit I2C 2 channels 8 bit CORE M8051 General purpose I O 46 ports normal I O Watchdog timer 1 channel 8 bit 128kHz internal RC OSC Basic interval timer 1 channel 8 bit Timer Counter 1 channel 8 bit 5 channels 16 bit ...

Page 17: ...description In this chapter A96G140 A96G148 A96A148 device pinouts and pin descriptions are introduced 2 1 Pinouts A96G140CL A96G148CL 48LQFP 0707 A96G140CU A96G148CU 48QFN 0606 NOTE Programmer E PGM E Gang4 6 uses P0 1 0 pin as DSCL DSDA Figure 2 A96G140 A96G148 48LQFP 48QFN Pin Assignment ...

Page 18: ...6G148SQ 44MQFP 1010 NOTES 1 The programmer E PGM E Gang4 6 uses P0 1 0 pin as DSCL DSDA 2 The P44 P47 pins should be selected as a push pull output or an input with pull up resistor by software control when the 44 pin package is used Figure 3 A96G140 A96G148 44MQFP 1010 Pin Assignment ...

Page 19: ... LQFP NOTES 1 The programmer E PGM E Gang4 6 uses P0 1 0 pin as DSCL DSDA 2 The P14 P17 P23 P25 P34 P37 and P43 P47 pins should be selected as a push pull output or an input with pull up resistor by software control when the 32 pin package is used Figure 4 A96G140 A96G148 32LQFP Pin Assignment ...

Page 20: ... pull output or an input with pull up resistor by software control when the 32 pin package is used Figure 5 A96G140 A96G148 32SOP Pin Assignment 1 2 13 14 8 9 10 11 12 3 4 5 6 7 16 15 21 20 19 18 17 26 25 24 23 22 28 27 P51 XIN P52 EINT8 EC0 P53 SXIN T0O PWM0O P54 SXOUT EINT10 VSS P50 XOUT P55 RESETB P40 RXD0 SCL0 MISO0 P41 TXD0 SDA0 MOSI0 P32 LED5 P31 LED6 P30 LED7 P42 SCK0 P33 LED4 P01 T3O PWM3O...

Page 21: ...P03 AN1 EINT1 P02 AN0 AVREF EINT0 T4O PWM4O P30 LED7 P20 AN14 TXD1 SDA1 MOSI1 VDD P05 AN3 EINT3 EC3 P04 AN2 EINT2 T3O PWM3O P07 AN5 EINT5 P11 AN12 EINT12 T2O PWM2O P12 AN11 EINT11 T1O PWM1O P10 AN13 RXD1 SCL1 MISO1 P06 AN4 EINT4 T5O PWM5O A96A148GD 28 SOP NOTES 3 The programmer E PGM E Gang4 6 uses P0 1 0 pin as DSCL DSDA 4 The P13 P17 P22 P27 P34 P37 and P43 P47 pins should be selected as a push ...

Page 22: ...ort 0 bit 2 Input output AN0 IA ADC input ch 0 AVREF P A D converter reference voltage EINT0 I External interrupt input ch 0 T4O O Timer 4 interval output PWM4O O Timer 4 PWM output 37 34 24 28 24 24 P03 IOUS Port 0 bit 3 Input output AN1 IA ADC input ch 1 EINT1 I External interrupt input ch 1 35 33 23 27 23 23 P04 IOUS Port 0 bit 4 Input output AN2 IA ADC input ch 2 EINT2 I External interrupt inp...

Page 23: ...US Port 1 bit 1 Input output AN12 IA ADC input ch 12 EINT12 I External interrupt input ch 12 T2O O Timer 2 interval output PWM2O O Timer 2 PWM output 26 24 18 22 19 19 P12 IOUS Port 1 bit 2 Input output AN11 IA ADC input ch 11 EINT11 I External interrupt input ch 11 T1O O Timer 1 interval output PWM1O O Timer 1 PWM output 27 25 19 23 P13 IOUS Port 1 bit 3 Input output AN10 IA ADC input ch 10 EC1 I...

Page 24: ...SI 21 20 14 18 15 P21 IOUS Port 2 bit 1 Input output AN15 IA ADC input ch 15 SCK1 IO USART1 clock signal 20 19 13 17 P22 IOUS Port 2 bit 2 Input output SS1 IO USART1 slave select signal 19 18 P23 IOU Port 2 bit 3 Input output 18 17 P24 IOU Port 2 bit 4 Input output 17 16 P25 IOU Port 2 bit 5 Input output 16 15 12 16 P26 IOU Port 2 bit 6 Input output 15 14 11 15 P27 IOU Port 2 bit 7 Input output 14...

Page 25: ...SART0 SPI MISO 3 3 5 9 9 P41 IOUS Port 4 bit 1 Input output TXD0 O USART0 data transmit SDA0 IO I2C data signal MOSI0 IO USART0 SPI MOSI 4 4 10 10 P42 IOUS Port 4 bit 2 Input output SCK0 IO USART0 clock signal 5 5 P43 IOUS Port 4 bit 3 Input output SS0 IO USART0 slave select signal 12 P44 IOUC Port 4 bit 4 Input output 24 P45 IOUC Port 4 bit 5 Input output 36 P46 IOUC Port 4 bit 6 Input output 48 ...

Page 26: ...e not in the 32 pin package 2 The P13 P17 P22 P27 P34 P37 and P43 P47 are not in the 28 pin package 3 The P43 is not in the 48 pin package 4 The P55 RESETB pin is configured as one of the P55 and RESETB pin by the CONFIGURE OPTION 5 If the P00 EC3 DSDA and P01 T3O DSCL pins are connected to the programmer during power on reset the pins are automatically configured as In system programming pins 6 T...

Page 27: ... respectively PULL UP REGISTER OPEN DRAIN REGISTER DATA REGISTER SUB FUNC DATA OUTPUT SUB FUNC ENABLE DIRECTION REGISTER SUB FUNC DIRECTION Q D r CP DEBOUNCE CLK DEBOUNCE ENABLE SUB FUNC DATA INPUT PORTx INPUT PAD VDD VDD VDD R 200 MUX MUX 0 1 MUX 0 1 0 1 MUX 0 1 CMOS or Schmitt Level Input Level Shift 1 8V to ExtVDD Level Shift ExtVDD to 1 8V ANALOG CHANNEL ENABLE ANALOG INPUT R 200 Figure 8 Gene...

Page 28: ... to 1 8V DATA REGISTER OPEN DRAIN REGISTER PULL UP REGISTER SUB FUNC DATA OUTPUT DIRECTION REGISTER SUB FUNC DIRECTION 0 1 MUX MUX 0 1 0 1 MUX r D CP Q DEBOUNCE CLK DEBOUNCE ENABLE PORTx INPUT SUB FUNC DATA INPUT ANALOG CHANNEL ENABLE ANALOG INPUT 0 1 MUX r D CP Q VDD EXTERNAL INTERRUPT INTERRUPT ENABLE EDGE REG FLAG CLEAR POLARITY REG R 400Ω CMOS or SchmittLevel Input ...

Page 29: ...e figure the M8051EW supports both Program Memory and External Data Memory In addition it features a Debug Mode in which it can be driven through a dedicated debug interface Figure 10 M8051EW Architecture Main features of the M8051EW are listed below Two clocks per machine cycle architecture This allows the device either to run up to six times faster with the same power consumption or to consume o...

Page 30: ...m interfaces Up to 256bytes of Internal Data Memory Up to 1Mbyte of RAM or ROM Program Memory accessible by selecting one from interfaces Support for synchronous and asynchronous Program External Data and Internal Data Memory Wait states support for slow Program and External Data Memory 16 bit Data Memory address is generated through the Data Pointer register DPTR register 16 bit program counter i...

Page 31: ...gisters Four banks of registers are available The current bank is selected by the 3rd and 4th bits of the PSW 4 Register specific addressing mode In this mode some instructions only operate on specific registers This is defined by the opcode In particular many accumulator operations and some stack pointer operations are defined in this manner 5 Immediate DATA mode In this mode Instructions which u...

Page 32: ...m Memory where this is implemented as RAM This instruction can also be used subsequently to modify contents of the Program Memory RAM Arithmetic Instruction The M8051EW implements ADD ADDC Add with Carry SUBB Subtract with Borrow INC Increment and DEC Decrement functions which can be used in most addressing modes There are three accumulator specific instructions DA A Decimal Adjust A MUL AB Multip...

Page 33: ...is instruction jumps to a location of which address is stored in DPTR register and offset by a value stored in the accumulator Subroutine calls and returns There are only two sorts of subroutine call ACALL and LCALL which are Absolute and Long Two return instructions are provided RET and RETI The latter is for interrupt service routines Conditional jumps All conditional jump instructions use relat...

Page 34: ...A148 has just 64Kbytes program memory space Figure 9 shows a map of the lower part of the program memory After reset CPU begins execution from location 0000H Each interrupt is assigned a fixed location in the program memory An interrupt causes the CPU to jump to the corresponding location where it commences execution of the service routine An external interrupt 11 for example is assigned to locati...

Page 35: ...emory space Thus as shown in figure 10 the upper 128bytes and SFR space occupy the same block of addresses 80H through FFH although they are physically separate entities The lower 128bytes of RAM are present in all 8051 devices as mapped in figure 11 The lowest 32bytes are grouped into 4 banks of 8 registers Program instructions call out these registers as R0 through R7 Two bits in the Program Sta...

Page 36: ...direct addressing The upper 128bytes of RAM can only be accessed by indirect addressing These spaces are used for data RAM and stack FFH 80H 7FH 00H FFH 80H Upper 128bytes Internal RAM Indirect Addressing Special Function Registers 128bytes Direct Addressing Lower 128bytes Internal RAM Direct or Indirect Addressing Figure 12 Data Memory Map ...

Page 37: ...43 42 41 40 3F 3E 3D 3C 3B 3A 39 38 37 36 35 34 33 32 31 30 2F 2E 2D 2C 2B 2A 29 28 27 26 25 24 23 22 21 20 1F 1E 1D 1C 1B 1A 19 18 17 16 15 14 13 12 11 10 0F 0E 0D 0C 0B 0A 09 08 07 06 05 04 03 02 01 00 80bytes 16bytes 128bits 8bytes 8bytes 8bytes 8bytes Register Bank 3 8bytes Register Bank 2 8bytes Register Bank 1 8bytes Register Bank 0 8bytes Figure 13 Lower 128bytes of RAM 5 3 External data me...

Page 38: ... compatible 00H 8H 1 01H 9H 02H 0AH 03H 0BH 04H 0CH 05H 0DH 06H 0EH 07H 0FH 0F8H IP1 UBAUD UDATA P5FSR 0F0H B USI1ST1 USI1ST2 USI1BD USI1SDHR USI1DR USI1SCLR USI1SCHR 0E8H RSTFR USI1CR1 USI1CR2 USI1CR3 USI1CR4 USI1SAR P3FSR P4FSR 0E0H ACC USI0ST1 USI0ST2 USI0BD USI0SDHR USI0DR USI0SCLR USI0SCHR 0D8H LVRCR USI0CR1 USI0CR2 USI0CR3 USI0CR4 USI0SAR P0DB P15DB 0D0H PSW P5IO P0FSRL P0FSRH P1FSRL P1FSRH ...

Page 39: ...ADCDRH 90H P2 P0OD P1OD P2OD P4OD P5PU WTCR BUZCR 88H P1 WTDR WTCNT SCCR BITCR BITCNT WDTCR WDTDR WDTCNT BUZDR 80H P0 SP DPL DPH DPL1 DPH1 LVICR PCON NOTE 00H 8H these registers are bit addressable Table 4 XSFR Map Summary 00H 8H 1 01H 9H 02H 0AH 03H 0BH 04H 0CH 05H 0DH 06H 0EH 07H 0FH 1078H 1070H 1068H 1060H 1058H 1050H 1048H 1040H 1038H XTFLSR 1030H 1028H FEARH FEARM FEARL FEDR FETR 1020H FEMR F...

Page 40: ...sic Interval Timer Counter Register BITCNT R 0 0 0 0 0 0 0 0 8DH Watch Dog Timer Control Register WDTCR R W 0 0 0 0 0 8EH Watch Dog Timer Data Register WDTDR W 1 1 1 1 1 1 1 1 Watch Dog Timer Counter Register WDTCNT R 0 0 0 0 0 0 0 0 8FH BUZZER Data Register BUZDR R W 1 1 1 1 1 1 1 1 90H P2 Data Register P2 R W 0 0 0 0 0 0 0 0 91H P0 Open drain Selection Register P0OD R W 0 0 0 0 0 0 0 0 92H P1 Op...

Page 41: ...0 0 0 0 0 ACH P0 Pull up Resistor Selection Register P0PU R W 0 0 0 0 0 0 0 0 ADH P1 Pull up Resistor Selection Register P1PU R W 0 0 0 0 0 0 0 0 AEH P2 Pull up Resistor Selection Register P2PU R W 0 0 0 0 0 0 0 0 AFH P3 Pull up Resistor Selection Register P3PU R W 0 0 0 0 0 0 0 0 B0H P5 Data Register P5 R W 0 0 0 0 0 0 B1H P1 Direction Register P1IO R W 0 0 0 0 0 0 0 0 B2H Timer 0 Control Registe...

Page 42: ...R W 0 0 0 0 0 0 0 0 CDH USART Control Register 3 UCTRL3 R W 0 0 0 0 0 0 0 CFH USART Status Register USTAT R W 1 0 0 0 0 0 0 0 D0H Program Status Word Register PSW R W 0 0 0 0 0 0 0 0 D1H P5 Direction Register P5IO R W 0 0 0 0 0 0 D2H P0 Function Selection Low Register P0FSRL R W 0 0 0 0 0 0 0 0 D3H P0 Function Selection High Register P0FSRH R W 0 0 0 0 0 0 0 0 D4H P1 Function Selection Low Registe...

Page 43: ...H USI1 Control Register 3 USI1CR3 R W 0 0 0 0 0 0 0 0 ECH USI1 Control Register 4 USI1CR4 R W 0 0 0 0 0 EDH USI1 Slave Address Register USI1SAR R W 0 0 0 0 0 0 0 0 EEH Port3 Function Selection Register P3FSR R W 0 0 0 0 0 0 0 0 EFH P4 Function Selection Register P4FSR R W 0 0 0 0 F0H B Register B R W 0 0 0 0 0 0 0 0 F1H USI1 Status Register 1 USI1ST1 R W 0 0 0 0 0 0 0 F2H USI1 Status Register 2 US...

Page 44: ...0 1011H Timer 5 Control Low Register T5CRL R W 0 0 0 0 0 0 1012H Timer 5 A Data High Register T5ADRH R W 1 1 1 1 1 1 1 1 1013H Timer 5 A Data Low Register T5ADRL R W 1 1 1 1 1 1 1 1 1014H Timer 5 B Data High Register T5BDRH R W 1 1 1 1 1 1 1 1 1015H Timer 5 B Data Low Register T5BDRL R W 1 1 1 1 1 1 1 1 1018H USART Control Register 4 UCTRL4 R W 0 0 0 0 0 1019H USART Floating Point Counter FPCR R W...

Page 45: ...Register SP Stack Pointer 81H 7 6 5 4 3 2 1 0 SP R W R W R W R W R W R W R W R W Initial value 07H SP Stack Pointer DPL Data Pointer Register Low 82H 7 6 5 4 3 2 1 0 DPL R W R W R W R W R W R W R W R W Initial value 00H DPL Data Pointer Low DPH Data Pointer Register High 83H 7 6 5 4 3 2 1 0 DPH R W R W R W R W R W R W R W R W Initial value 00H DPH Data Pointer High DPL1 Data Pointer Register Low 1...

Page 46: ...urpose User Definable Flag RS1 Register Bank Select bit 1 RS0 Register Bank Select bit 0 OV Overflow Flag F1 User Definable Flag P Parity Flag Set Cleared by hardware each instruction cycle to indicate an odd even number of 1 bits in the accumulator EO Extended Operation Register A2H 7 6 5 4 3 2 1 0 TRAP_EN DPSEL2 DPSEL1 DPSEL0 R W R W R W R W Initial value 00H TRAP_EN Select the Instruction Keep ...

Page 47: ... set by a system reset 6 1 3 Pull up register selection register PxPU The on chip pull up resistor can be connected to I O ports individually with a pull up resistor selection register PxPU The pull up register selection controls the pull up resister enable disable of each port When the corresponding bit is 1 the pull up resister of the pin is enabled When 0 the pull up resister is disabled All bi...

Page 48: ... D5H R W 00H P1 Function Selection High Register P1FSRL D4H R W 00H P1 Function Selection Low Register P2 90H R W 00H P2 Data Register P2IO B9H R W 00H P2 Direction Register P2PU AEH R W 00H P2 Pull up Resistor Selection Register P2OD 93H R W 00H P2 Open drain Selection Register P2FSR D6H R W 00H P2 Function Selection Register P3 98H R W 00H P3 Data Register P3IO C1H R W 00H P3 Direction Register ...

Page 49: ...ister 80H 7 6 5 4 3 2 1 0 P07 P06 P05 P04 P03 P02 P01 P00 R W R W R W R W R W R W R W R W Initial value 00H P0 7 0 I O Data P0IO P0 Direction Register A1H 7 6 5 4 3 2 1 0 P07IO P06IO P05IO P04IO P03IO P02IO P01IO P00IO R W R W R W R W R W R W R W R W Initial value 00H P0IO 7 0 P0 Data I O Direction 0 Input 1 Output NOTES EC3 P00 EINT0 to EINT5 function possible when input EC3 P05 possible when P0F...

Page 50: ... 1 fx 4 1 0 fx 4096 1 1 LSIRC 128KHz P07DB Configure De bounce of P07 Port 0 Disable 1 Enable P06DB Configure De bounce of P06 Port 0 Disable 1 Enable P05DB Configure De bounce of P05 Port 0 Disable 1 Enable P04DB Configure De bounce of P04 Port 0 Disable 1 Enable P03DB Configure De bounce of P03Port 0 Disable 1 Enable P02DB Configure De bounce of P02 Port 0 Disable 1 Enable NOTES 1 If the same le...

Page 51: ...e when input 0 1 reserved 1 0 AN5 Function 1 1 Reserved P0FSRH 5 4 P06 Function Select P0FSRH5 P0FSRH4 Description 0 0 I O Port EINT4 function possible when input 0 1 reserved 1 0 AN4 Function 1 1 PWM5O T5O Function P0FSRH 3 2 P05 Function Select P0FSRH3 P0FSRH2 Description 0 0 I O Port EINT3 function possible when input 0 1 EC3 Function 1 0 AN3 Function 1 1 reserved P0FSRH 1 0 P04 Function Select...

Page 52: ...VREF Function 1 0 AN0 Function 1 1 T4O PWM4O Function P0FSRL 3 2 P01 Function Select P0FSRL3 P0FSRL2 Description 0 0 I O Port 0 1 T3O PWM3O Function 1 0 reserved 1 1 TXD2 Function P0FSRL 1 0 P00 Function Select P0FSRL1 P0FSRL0 Description 0 0 I O Port EC3 function possible when input 0 1 reserved 1 0 reserved 1 1 RXD2 Function 6 3 P1 port 6 3 1 P1 port description P1 is an 8 bit I O port P1 contro...

Page 53: ...O Direction 0 Input 1 Output NOTE EINT6 EINT7 EINT11 EINT12 EC1 function possible when input P1PU P1 Pull up Resistor Selection Register ADH 7 6 5 4 3 2 1 0 P17PU P16PU P15PU P14PU P13PU P12PU P11PU P10PU R W R W R W R W R W R W R W R W Initial value 00H P1PU 7 0 Configure Pull up Resistor of P1 Port 0 Disable 1 Enable P1OD P1 Open drain Selection Register 92H 7 6 5 4 3 2 1 0 P17OD P16OD P15OD P14...

Page 54: ...f P16 Port 0 Disable 1 Enable P12DB Configure De bounce of P12 Port 0 Disable 1 Enable P11DB Configure De bounce of P11 Port 0 Disable 1 Enable NOTES 1 If the same level is not detected on enabled pin three or four times in a row at the sampling clock the signal is eliminated as noise 2 A pulse level should be input for the duration of 3 clock or more to be actually detected as a valid edge 3 The ...

Page 55: ...ption 0 0 I O Port EINT6 function possible when input 0 1 reserved 1 0 AN6 Function 1 1 SS2 Function P1FSRH 5 4 P16 Function Select P1FSRH5 P1FSRH4 Description 0 0 I O Port EINT7 function possible when input 0 1 reserved 1 0 AN7 Function 1 1 XCK Function P1FSRH 3 2 P15 Function Select P1FSRH3 P1FSRH2 Description 0 0 I O Port 0 1 reserved 1 0 AN8 Function 1 1 MISO2 RXD2 P1FSRH 1 0 P14 Function Sele...

Page 56: ...input 0 1 reserved 1 0 AN11 Function 1 1 T1O PWM1O Function P1FSRL 3 2 P11 Function Select P1FSRL3 P1FSRL2 Description 0 0 I O Port EINT12 function possible when input 0 1 reserved 1 0 AN12 Function 1 1 T2O PWM2O Function P1FSRL 1 0 P10 Function Select P1FSRL1 P1FSRL0 Description 0 0 I O Port 0 1 reserved 1 0 AN13 Function 1 1 RXD1 SCL1 MISO1 Function 6 4 P2 port 6 4 1 P2 port description P2 is an...

Page 57: ...al value 00H P2IO 7 0 P2 Data I O Direction 0 Input 1 Output P2PU P2 Pull up Resistor Selection Register AEH 7 6 5 4 3 2 1 0 P27PU P26PU P25PU P24PU P23PU P22PU P21PU P20PU R W R W R W R W R W R W R W R W Initial value 00H P2PU 7 0 Configure Pull up Resistor of P2 Port 0 Disable 1 Enable P2OD P2 Open drain Selection Register 93H 7 6 5 4 3 2 1 0 P27OD P26OD P25OD P24OD P23OD P22OD P21OD P20OD R W R...

Page 58: ...SR 1 0 P20 Function Select P2FSR1 P2FSR0 Description 0 0 I O Port 0 1 reserved 1 0 AN14 Function 1 1 TXD1 SDA1 MOSI1 Function 6 5 P3 port 6 5 1 P3 port description P3 is an 8 bit I O port P3 control registers consist of P3 data register P3 P3 direction register P3IO and P3 pull up resistor selection register P3PU Refer to the port function selection registers for the P3 function selection 6 5 2 Re...

Page 59: ...P31IO P30IO R W R W R W R W R W R W R W R W Initial value 00H P3IO 7 0 P3 Data I O Direction 0 Input 1 Output P3PU P3 Pull up Resistor Selection Register AFH 7 6 5 4 3 2 1 0 P37PU P36PU P35PU P34PU P33PU P32PU P31PU P30PU R W R W R W R W R W R W R W R W Initial value 00H P3PU 7 0 Configure Pull up Resistor of P3 Port 0 Disable 1 Enable ...

Page 60: ...P33 Function select 0 I O Port 1 LED4 Function P3FSR2 P32 Function Select 0 I O Port 1 LED5 Function P3FSR1 P31 Function select 0 I O Port 1 LED6 Function P3FSR0 P30 Function Select 0 I O Port 1 LED7 Function NOTE LEDn function is used for high current driving and it can drive about 180mA Typ VDD 5V VOL 1 5V 6 6 P4 port 6 6 1 P4 port description P4 is a 4 bit I O port P4 control registers consist ...

Page 61: ...al value 00H P4IO 7 0 P4 Data I O Direction 0 Input 1 Output P4PU P4 Pull up Resistor Selection Register A3H 7 6 5 4 3 2 1 0 P47PU P46PU P45PU P44PU P43PU P42PU P41PU P40PU R W R W R W R W R W R W R W R W Initial value 00H P4PU 3 0 Configure Pull up Resistor of P4 Port 0 Disable 1 Enable P4OD P4 Open drain Selection Register 94H 7 6 5 4 3 2 1 0 P47OD P46OD P45OD P44OD P43OD P42OD P41OD P40OD R W R...

Page 62: ...7 1 P5 port description P5 is a 6 bit I O port P5 control registers consist of P5 data register P5 P5 direction register P5IO andP5 pull up resistor selection register P5PU Refer to the port function selection registers for the P5 function selection 6 7 2 Register description for P5 P5 P5 Data Register B0H 7 6 5 4 3 2 1 0 P55 P54 P53 P52 P51 P50 R W R W R W R W R W R W Initial value 00H P5 5 0 I O...

Page 63: ...ial value 00H P5FSR 7 6 P54 Function Select P5FSR7 P5FSR6 Description 0 0 I O Port EINT10 function possible when input 0 1 SXOUT Function 1 0 reserved 1 1 reserved P5FSR 5 4 P53 Function Select P5FSR5 P5FSR4 Description 0 0 I O Port 0 1 SXIN Function 1 0 T0O PWM0O Function 1 1 reserved P5FSR 3 2 P51 Function Select P5FSR3 P5FSR2 Description 0 0 I O Port 0 1 XIN Function 1 0 reserved 1 1 reserved P...

Page 64: ...h four pairs of interrupt enable registers IE IE1 IE2 and IE3 Each bit of IE IE1 IE2 IE3 register individually enables disables the corresponding interrupt source Overall control is provided by bit 7 of IE EA When EA is set to 0 all interrupts are disabled when EA is set to 1 interrupts are individually enabled or disabled through the other bits of the interrupt enable registers The EA bit is alwa...

Page 65: ...2 Interrupt 5 Interrupt 11 Interrupt 17 Interrupt 23 Highest Lowest Highest Lowest Figure 15 Interrupt Group Priority Level 7 1 External interrupt External interrupts on INT0 INT1 INT5 INT6 and INT11 pins receive various interrupt requests depending on the external interrupt polarity 0 high low register EIPOL0H L and external interrupt polarity 1 register EIPOL1 as shown in figure 14 Each external...

Page 66: ... FLAG1 EINT2 Pin FLAG2 FLAG3 EINT4 Pin FLAG4 FLAG5 EINT6 Pin FLAG6 FLAG7 EINT11 Pin FLAG11 EINT12 Pin FLAG12 EIPOL1 2 2 EIPOL0H EIPOL0L 2 2 2 2 2 2 INT1 Interrupt INT11 Interrupt INT5 Interrupt EINT10 Pin FLAG10 2 INT0 Interrupt EINT8 Pin FLAG8 2 INT6 Interrupt Figure 16 External Interrupt Description 7 2 Block diagram ...

Page 67: ... Timer 0 overflow Timer 0 Timer 1 Timer 2 Timer 3 IP1 IP IE FLAG10 FLAG11 IE2 T0OVIFR T0IFR T1IFR T2IFR T3IFR FLAG0 FLAG1 FLAG2 FLAG3 FLAG4 FLAG5 FLAG6 FLAG7 EIPOL1 USI0 I2C USI0 Rx USI0 Tx IE1 I2C0IFR ADC WT WDT BIT ADCIFR WTIFR WDTIFR BITIFR Level 0 Level 1 Level 2 Level 3 EIPOL0H L USI1 I2C USI1 Rx USI1 Tx I2C1IFR USART2 RX EINT12 EIFLAG1 3 FLAG12 EIPOL1 IE3 EINT8 EIFLAG1 0 FLAG8 EIPOL1 Timer 4...

Page 68: ...ble 0033H USART2 TX Interrupt INT7 IE1 1 8 Maskable 003BH USI0 I2C Interrupt INT8 IE1 2 9 Maskable 0043H USI0 Rx Interrupt INT9 IE1 3 10 Maskable 004BH USI0 Tx Interrupt INT10 IE1 4 11 Maskable 0053H External Interrupt 12 INT11 IE1 5 12 Maskable 005BH T0 Overflow Interrupt INT12 IE2 0 13 Maskable 0063H T0 Match Interrupt INT13 IE2 1 14 Maskable 006BH T1 Match Interrupt INT14 IE2 2 15 Maskable 0073...

Page 69: ...cceptance always generates at last cycle of the instruction So instead of fetching the current instruction CPU executes internally LCALL instruction and saves the PC at stack For the interrupt service routine the interrupt controller gives the address of LJMP instruction to CPU Since the end of the execution of current instruction it needs 3 to 9 machine cycles to go to the interrupt service routi...

Page 70: ... IE3 Saves PC value in order to continue process again after executing ISR IE EA Flag 0 1 Program Counter low Byte SP SP 1 M SP PCL 2 Program Counter high Byte SP SP 1 M SP PCH 3 Interrupt Vector Address occurrence Interrupt Vector Address 4 ISR Interrupt Service Routine move execute 5 Return from ISR RETI 6 Program Counter high Byte recovery PCH M SP SP SP 1 7 Main Program execution 10 Program Co...

Page 71: ...imultaneously the request of higher priority level is served first If more than one interrupt request are received the interrupt polling sequence determines which request is served first by hardware However for special features multi interrupt processing can be executed by software Interrupt Enable Register command Next Instruction Next Instruction After executing IE set clear enable register is e...

Page 72: ...erved after the INT1 service has completed An interrupt service routine may be only interrupted by an interrupt of higher priority and if two interrupts of different priority occur at the same time the higher level interrupt will be served first An interrupt cannot be interrupted by another interrupt of the same or a lower priority level If two interrupts of the same priority level occur simultane...

Page 73: ... the Entry Address of ISR 7 9 Saving restore general purpose registers Figure 24 Saving Restore Process Diagram and Sample Source Interrupt latched Interrupt goes active System Clock Max 4 Machine Cycle 4 Machine Cycle Interrupt Processing LCALL LJMP Interrupt Routine 0EH 2EH 0125H 0126H Basic Interval Timer Service Routine Address Basic Interval Timer Vector Table Address 00B3H 00B4H 02H 25H 01H ...

Page 74: ...tes long call to jump to interrupt service routine 7 11 Interrupt register overview 7 11 1 Interrupt Enable Register IE IE1 IE2 and IE3 Interrupt enable register consists of global interrupt control bit EA and peripheral interrupt control bits Total 24 peripherals are able to control interrupt 7 11 2 Interrupt Priority Register IP and IP1 24 interrupts are divided into 6 groups which have 4 interr...

Page 75: ...IPOL0H L and External Interrupt Polarity1 Register EIPOL1 determines an edge type from rising edge falling edge and both edges of interrupt Initially default value is no interrupt at any edge 7 11 5 Register map Table 9 Interrupt Register Map Name Address Direction Default Description IE A8H R W 00H Interrupt Enable Register IE1 A9H R W 00H Interrupt Enable Register 1 IE2 AAH R W 00H Interrupt Ena...

Page 76: ...Interrupt disable 1 All Interrupt enable INT5E Enable or Disable External Interrupt 0 7 EINT0 EINT7 0 Disable 1 Enable INT4E Enable or Disable USI1 Tx Interrupt 0 Disable 1 Enable INT3E Enable or Disable USI1 Rx Interrupt 0 Disable 1 Enable INT2E Enable or Disable USI1 I2C Interrupt 0 Disable 1 Enable INT1E Enable or Disable External Interrupt 11 EINT11 0 Disable 1 Enable INT0E Enable or Disable E...

Page 77: ...00H INT11E Enable or Disable External Interrupt 12 EINT12 0 Disable 1 Enable INT10E Enable or Disable USI0Tx Interrupt 0 Disable 1 Enable INT9E Enable or Disable USI0 Rx Interrupt 0 Disable 1 Enable INT8E Enable or Disable USI0 I2C Interrupt 0 Disable 1 Enable INT7E Enable or Disable USART2 TX Interrupt 0 Disable 1 Enable INT6E Enable or Disable External Interrupt 8 EINT8 0 Disable 1 Enable ...

Page 78: ... Enable or Disable Timer 4 5 Match Interrupt 0 Disable 1 Enable INT16E Enable or Disable Timer 3 Match Interrupt 0 Disable 1 Enable INT15E Enable or Disable Timer 2 Match Interrupt 0 Disable 1 Enable INT14E Enable or Disable Timer 1 Match Interrupt 0 Disable 1 Enable INT13E Enable or Disable Timer 0 I Match Interrupt 0 Disable 1 Enable INT12E Enable or Disable Timer 0 Overflow Interrupt 0 Disable ...

Page 79: ...le 1 Enable INT20E Enable or Disable WT Interrupt 0 Disable 1 Enable INT19E Enable or Disable USART2 RX Interrupt 0 Disable 1 Enable INT18E Enable or Disable ADC Interrupt 0 Disable 1 Enable IP Interrupt Priority Register B8H 7 6 5 4 3 2 1 0 IP5 IP4 IP3 IP2 IP1 IP0 R W R W R W R W R W R W Initial value 00H IP1 Interrupt Priority Register 1 F8H 7 6 5 4 3 2 1 0 IP15 IP14 IP13 IP12 IP11 IP10 R W R W ...

Page 80: ... 3 2 1 0 POL7 POL6 POL5 POL4 R W R W R W R W R W R W R W R W Initial value 00H EIPOL0H 7 0 External interrupt EINT7 EINT6 EINT5 EINT4 polarity selection POLn 1 0 Description 0 0 No interrupt at any edge 0 1 Interrupt on rising edge 1 0 Interrupt on falling edge 1 1 Interrupt on both of rising and falling edge Where n 4 5 6 and 7 EIPOL0L External Interrupt Polarity 0Low Register A4H 7 6 5 4 3 2 1 0...

Page 81: ...by INT_ACK signal Writing 1 has no effect 0 T0 Interrupt no generation 1 T0 Interrupt generation EIFLAG1 3 0 When an External Interrupt EINT8 EINT10 EINT12 is occurred the flag becomes 1 The flag is cleared by writing 0 to the bit or automatically cleared by INT_ACK signal Writing 1 has no effect 0 External Interrupt not occurred 1 External Interrupt occurred EIPOL1 External Interrupt Polarity 1 R...

Page 82: ...ce external clock signal into the XIN SXIN pin and open XOUT SXOUT pin Default system clock is 1MHz INT RC Oscillator To stabilize the system internally 128KHz LOW INT RC oscillator on POR is recommended Oscillators in the clock generator are introduced in the followings Calibrated high internal RC oscillator 32MHz HSIRC OSC 2 16MHz default system clock HSIRC OSC 4 8MHz HSIRC OSC 8 4MHz HSIRC OSC ...

Page 83: ... 26 Clock Generator Block Diagram 8 2 Register map Table 10 Clock Generator Register Map Name Address Direction Default Description SCCR 8AH R W 00H System and Clock Control Register OSCCR C8H R W 28H Oscillator Control Register XTFLSR 1038H R W 00H Main Crystal OSC Filter Selection Register 8 3 Register description SCCR System and Clock Control Register 8AH 7 6 5 4 3 2 1 0 SCLK1 SCLK0 R W R W Ini...

Page 84: ...ost divider Selection IRCS2 IRCS1 IRCS0 Description 0 0 0 INT RC 64 0 5MHz 0 0 1 INT RC 32 1MHz 0 1 0 INT RC 16 2MHz 0 1 1 INT RC 8 4MHz 1 0 0 INT RC 4 8MHz 1 0 1 INT RC 2 16MHz 1 1 0 Test only Other Values reserved HSIRCE Control the Operation of the High Frequency 32MHz Internal RC Oscillator 0 Enable operation of HSIRC OSC 1 Disable operation of HSIRC OSC XCLKE Control the Operation of the Exte...

Page 85: ...ns 4MHz MX_FIL_DIS Main X TAL noise canceller selection 0 Using noise filter 1 Bypass noise filter MX_ISEL 1 0 Current selective option for MX TAL MX_ISEL1 MX_ISEL0 Description 0 0 HIGH 12M 0 1 MID HIGH 8 12M 1 0 MID LOW 4 8M 1 1 LOW 4M SUB_FIL_DIS SUB X TAL noise canceller selection 0 Using noise filter 1 Bypass noise filter SUB_ISEL 1 0 Current selective option for SUB TAL SUB_ISEL1 SUB_ISEL0 De...

Page 86: ... 9 1 BIT block diagram In this section basic interval timer of A96G140 A96G148 A96A148 is described in a block diagram 32 Prescaler 1 4096 1 16 1 1024 1 128 3 BITCK BITCNT BITIFR Overflow 8 bit up counter BITCR INT_ACK From CPU Interal BUS line BCLR Read BIT Interrupt WDT Source Clock 8BH 8CH fx System Clock LIRC OSC 128kHz BIT_CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 BITR BIT_Int_...

Page 87: ... bit becomes 1 For clearing bit write 0 to this bit or auto clear by INT_ACK signal Writing 1 has no effect 0 BIT interrupt no generation 1 BIT interrupt generation BITCK 2 0 Select BIT clock source BITCK2 BITCK1 BITCK0 Description 0 0 0 fx 4096 0 0 1 fx 1024 0 1 0 fx 128 0 1 1 fx 16 1 Other Values LSIRC 32 Default BCLR If this bit is written to 1 BIT Counter is cleared to 0 0 Free Running 1 Clear...

Page 88: ...ing WDTCR 6 bit If WDTCR 5 is set to 1 the WDT counter value is cleared and counts up After 1 machine cycle this bit is cleared to 0 automatically The WDT consists of an 8 bit binary counter and a watchdog timer data register When value of the 8 bit binary counter is equal to the 8 bits of WDTCNT an interrupt request flag is generated This can be used as a watchdog timer interrupt or a reset signa...

Page 89: ...8 WDTCK Figure 29 Watch Dog Timer Block Diagram 10 3 Register map Table 12 Watchdog Timer Register Map Name Address Direction Default Description WDTCNT 8EH R 00H Watch Dog Timer Counter Register WDTDR 8EH W FFH Watch Dog Timer Data Register WDTCR 8DH R W 00H Watch Dog Timer Control Register 10 4 Register description WDTCNT Watch Dog Timer Counter Register Read Case 8EH 7 6 5 4 3 2 1 0 WDTCNT7 WDT...

Page 90: ...3 2 1 0 WDTEN WDTRSON WDTCL WDTCK WDTIFR R W R W R W R W R W Initial value 00H WDTEN Control WDT Operation 0 Disable 1 Enable WDTRSON Control WDT RESET Operation 0 Free Running 8 bit timer 1 Watch Dog Timer RESET ON WDTCL Clear WDT Counter 0 Free Run 1 Clear WDT Counter auto clear after 1 Cycle WDTCK Control WDT Clock Selection Bit 0 BIT overflow for WDT clock 1 BIT overflow 8 for WDT clock WDTIFR...

Page 91: ...unter circuits may be composed of 21 bit counter which contains low 14 bit with binary counter and high 7 bit counter in order to increase resolution In WTDR it can control WT clear and set interval value at write time and it can read 7 bit WT counter value at read time 11 1 WT block diagram In this section watch timer of A96G140 A96G148 A96A148 is described in a block diagram P r e s c a l e r fx...

Page 92: ...WTCNT Watch Timer Counter Register Read Case 89H 7 6 5 4 3 2 1 0 WTCNT6 WTCNT5 WTCNT4 WTCNT3 WTCNT2 WTCNT1 WTCNT0 R R R R R R R Initial value 00H WTCNT 6 0 WT Counter WTDR Watch Timer Data Register Write Case 89H 7 6 5 4 3 2 1 0 WTCL WTDR6 WTDR5 WTDR4 WTDR3 WTDR2 WTDR1 WTDR0 R W W W W W W W W Initial value 7FH WTCL Clear WT Counter 0 Free Run 1 Clear WT Counter auto clear after 1 Cycle WTDR 6 0 Se...

Page 93: ...te 0 to this bit or automatically clear by INT_ACK signal Writing 1 has no effect 0 WT Interrupt no generation 1 WT Interrupt generation WTIN 1 0 Determine interrupt interval WTIN1 WTIN0 Description 0 0 fWCK 2 7 0 1 fWCK 2 13 1 0 fWCK 2 14 1 1 fWCK 2 14 x 7bit WTDR Value 1 WTCK 1 0 Determine Source Clock WTCK1 WTCK0 Description 0 0 fSUB 0 1 fX 256 1 0 fX 128 1 1 fX 64 NOTES 1 fX System clock frequ...

Page 94: ... T0DR T0O port toggles In addition timer 0 outputs PWM waveform through PWM0O port in the PWM mode Table 14 Timer 0 Operating Mode T0EN T0MS 1 0 T0CK 2 0 Timer 0 1 00 XXX 8 bit Timer Counter Mode 1 01 XXX 8 bit PWM Mode 1 1X XXX 8 bit Capture Mode 12 1 1 8 bit timer counter mode As shown in figure 29 8 bit timer counter mode is selected by control register 8 bit timer has counter and data register...

Page 95: ...2 0 T0EN 8 bit Timer 0 Counter T0DR 8Bit Comparator T0IFR T0O PWM0O 8 bit Timer 0 Data Register INT_ACK Clear Match signal Clear Match MUX T0MS 1 0 2 To interrupt block T0EN T0MS1 T0MS0 T0CK2 T0CK1 T0CK0 T0CC T0CR 1 0 0 x x x x ADDRESS B2H INITIAL VALUE 0000_0000B T0CC Figure 31 8 bit Timer Counter Mode for Timer 0 Figure 32 8 bit Timer Counter 0 Example ...

Page 96: ...upt of timer 0 occurs In PWM mode the match signal does not clear the counter Instead it runs continuously overflowing at FFH Then the counter continues incrementing from 00H The timer 0 overflow interrupt is generated whenever a counter overflow occurs T0CNT value is cleared by software T0CC bit P r e s c a l e r fx M U X fx 2 T0CNT 8Bit EC0 fx 4 fx 8 fx 32 fx 128 fx 512 fx 2048 3 T0CK 2 0 T0EN 8...

Page 97: ... T0CNT T0PWM 00H 01H 02H 4AH FFH FEH 00H T0 Match Interrupt T0 Overflow Interrupt T0DR 1 T0DR 4AH Timer 0 clock Set T0EN T0PWM T0 Match Interrupt 2 T0DR 00H T0PWM T0 Match Interrupt 3 T0DR FFH PWM Mode T0MS 01b Figure 34 PWM Output Waveforms in PWM Mode for Timer 0 ...

Page 98: ...e timer 0 output T0O waveform is not available According to EIPOL1 registers setting the external interrupt EINT10 function is chosen Of course the EINT10 pin must be set to an input port T0CDR and T0DR are in the same address In the capture mode reading operation readsT0CDR not T0DR and writing operation will update T0DR P r e s c a l e r fx M U X fx 2 T0CNT 8Bit EC0 fx 4 fx 8 fx 32 fx 128 fx 512...

Page 99: ...A96G140 A96G148 A96A148 User s manual 12 Timer 0 1 2 3 4 5 99 Figure 36 Input Capture Mode Operation for Timer 0 Figure 37 Express Timer Overflow in Capture Mode ...

Page 100: ...0 EIPOL1 1 0 FLAG10 EIFLAG1 0 INT_ACK Clear To interrupt block 2 T0MS 1 0 2 T0MS 1 0 2 Match signal T0CC Figure 38 8 bit Timer 0 Block Diagram 12 1 5 Register map Table 15 Timer 0 Register Map Name Address Direction Default Description T0CNT B3H R 00H Timer 0 Counter Register T0DR B4H R W FFH Timer 0 Data Register T0CDR B4H R 00H Timer 0 Capture Data Register T0CR B2H R W 00H Timer 0 Control Regis...

Page 101: ...T0CK0 T0CC R W R W R W R W R W R W R W Initial value 00H T0EN Control Timer 0 0 Timer 0 disable 1 Timer 0 enable T0MS 1 0 Control Timer 0 Operation Mode T0MS1 T0MS0 Description 0 0 Timer counter mode 0 1 PWM mode 1 x Capture mode T0CK 2 0 Select Timer 0 clock source fx is a system clock frequency T0CK2 T0CK1 T0CK0 Description 0 0 0 fx 2 0 0 1 fx 4 0 1 0 fx 8 0 1 1 fx 32 1 0 0 fx 128 1 0 1 fx 512 1...

Page 102: ... mode In addition Timer 1 outputs PWM waveform through PWM1Oport in the PPG mode Table 16 TIMER 1 Operating Modes T1EN P1FSRL 5 4 T1MS 1 0 T1CK 2 0 Timer 1 1 11 00 XXX 16 Bit Timer Counter Mode 1 00 01 XXX 16 Bit Capture Mode 1 11 10 XXX 16 Bit PPG Mode one shot mode 1 11 11 XXX 16 Bit PPG Mode repeat mode 12 2 1 16 bit timer counter mode 16 bit timer counter mode is selected by control registers ...

Page 103: ...T1CNTL Clear Edge Detector T1ECE EC1 Comparator 16 bit A Data Register T1ADRH T1ADRL T1IFR INT_ACK Clear To interrupt block A Match Buffer Register A A Match T1CC Reload Pulse Generator T1O R T1EN 3 T1CK 2 0 2 T1MS1 T1MS0 T1CC 0 0 X T1CK2 T1CRL X ADDRESS BAH INITIAL VALUE 0000_0000B T1CK1 T1CK0 T1IFR T1POL T1ECE T1CNTR X X X X X X T1EN Figure 39 16 bit Timer Counter Mode of Timer 1 Figure 40 16 bi...

Page 104: ...RH T1BDRL According to EIPOL1 registers setting the external interrupt EINT11 function is selected EINT11 pin must be set as an input port A Match T1CC T1EN P r e s c a l e r fx M U X fx 2 fx 4 fx 64 fx 512 fx 2048 fx 8 fx 1 16 bit Counter T1CNTH T1CNTL 16 bit B Data Register T1BDRH T1BDRL Clear Edge Detector T1ECE EC1 Comparator 16 bit A Data Register T1ADRH T1ADRL T1IFR INT_ACK Clear To interrup...

Page 105: ... TIMER 1 has a PPG Programmable Pulse Generation function In PPG mode T1O PWM1O pin outputs up to 16 bit resolution PWM output For this function T1O PWM1O pin must be configured as a PWM output by setting P1FSRL 5 4 to 11 Period of the PWM output is determined by T1ADRH T1ADRL and duty of the PWM output is determined by T1BDRH T1BDRL ...

Page 106: ...mparator 16 bit A Data Register T1ADRH T1ADRL T1IFR INT_ACK Clear To interrupt block A Match Buffer Register A Reload Pulse Generator T1O PWM1O R T1EN 3 T1CK 2 0 2 T1EN T1CRH 1 ADDRESS BBH INITIAL VALUE 0000_0000B T1MS1 T1MS0 T1CC 1 1 X T1CK2 T1CRL X ADDRESS BAH INITIAL VALUE 0000_0000B T1CK1 T1CK0 T1IFR T1POL T1ECE T1CNTR X X X X X X A Match T1CC T1EN A Match T1CC T1EN NOTE T1EN is automatically ...

Page 107: ... 3 7 2 M A Match 1 T1BDRH L 5 T1ADRH L PWM1O A Match 2 T1BDRH L T1ADRH L PWM1O A Match 3 T1BDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 0 Timer 1 clock Counter T1ADRH L T1 Interrupt PWM1O B Match One shot Mode T1MS 10b and Start High T1POL 0b Set T1EN 0 Clear and Start 3 7 M A Match 1 T1BDRH L 5 T1ADRH L PWM1O A Match 2 T1BDRH L T1ADRH L PWM1O A Match 3 T1BDRH L 0000H Low Level Figure 44 16 bit PPG Mo...

Page 108: ...er Register A Reload Pulse Generator T1O PWM1O R EINT11 T1CNTR T1EN 3 T1CK 2 0 Clear EIPOL1 5 4 FLAG11 EIFLAG1 2 INT_ACK Clear To interrupt block 2 2 T1MS 1 0 2 Edge Detector T1ECE EC1 To Timer 2 block A Match T1CC T1EN A Match T1CC T1EN Figure 45 16 bit Timer 1 Block Diagram 12 2 5 Register map Table 17 TIMER 1 Register Map Name Address Direction Default Description T1ADRH BDH R W FFH Timer 1 A D...

Page 109: ...L2 T1ADRL1 T1ADRL0 R W R W R W R W R W R W R W R W Initial value FFH T1ADRL 7 0 T1 A Data Low Byte NOTE Do not write 0000H in the T1ADRH T1ADRL register when PPG mode T1BDRH Timer 1 B Data High Register BFH 7 6 5 4 3 2 1 0 T1BDRH7 T1BDRH6 T1BDRH5 T1BDRH4 T1BDRH3 T1BDRH2 T1BDRH1 T1BDRH0 R W R W R W R W R W R W R W R W Initial value FFH T1BDRH 7 0 T1 B Data High Byte T1BDRL Timer 1 B Data Low Regist...

Page 110: ...Timer 1 disable 1 Timer 1 enable Counter clear and start T1MS 1 0 Control Timer 1 Operation Mode T1MS1 T1MS0 Description 0 0 Timer counter mode T1O toggle at A match 0 1 Capture mode The A match interrupt can occur 1 0 PPG one shot mode PWM1O 1 1 PPG repeat mode PWM1O T1CC Clear Timer 1 Counter 0 No effect 1 Clear the Timer 1 counter When write automatically cleared 0 after being cleared counter ...

Page 111: ...ation 1 T1 Interrupt generation T1POL T1O PWM1O Polarity Selection 0 Start High T1O PWM1O is low level at disable 1 Start Low T1O PWM1O is high level at disable T1ECE Timer 1 External Clock Edge Selection 0 External clock falling edge 1 External clock rising edge T1CNTR Timer 1 Counter Read Control 0 No effect 1 Load the counter value to the B data register When write automatically cleared 0 after...

Page 112: ...Operating Modes T2EN P1FSRL 3 2 T2MS 1 0 T2CK 2 0 Timer 2 1 11 00 XXX 16 Bit Timer Counter Mode 1 00 01 XXX 16 Bit Capture Mode 1 11 10 XXX 16 Bit PPG Mode one shot mode 1 11 11 XXX 16 Bit PPG Mode repeat mode 12 3 1 16 bit timer counter mode 16 bit timer counter mode is selected by control registers and the 16 bit timer counter has counter registers and data registers as shown in figure 44 The co...

Page 113: ... INT_ACK Clear To interrupt block A Match Buffer Register A Reload Pulse Generator T2O R T2EN 3 T2CK 2 0 2 A Match T2CC T2EN T2EN T2CRH 1 ADDRESS C3H INITIAL VALUE 0000_0000B T2MS1 T2MS0 T2CC 0 0 X T2CK2 T2CRL X ADDRESS C2H INITIAL VALUE 0000_0000B T2CK1 T2CK0 T2IFR T2POL T2CNTR X X X X X NOTE T1 A Match is a pulse for the timer 2 clock source if it is selected Figure 46 16 bit Timer Counter Mode ...

Page 114: ...mer 2 output T2O waveform is not available According to EIPOL1 registers setting the external interrupt EINT12 function is selected EINT12 pin must be set as an input port A Match T2CC T2EN P r e s c a l e r fx M U X fx 2 fx 4 fx 32 fx 128 fx 512 fx 8 fx 1 16 bit Counter T2CNTH T2CNTL 16 bit B Data Register T2BDRH T2BDRL Clear T1 A Match Comparator 16 bit A Data Register T2ADRH T2ADRL T2IFR INT_AC...

Page 115: ...A96G140 A96G148 A96A148 User s manual 12 Timer 0 1 2 3 4 5 115 Figure 49 16 bit Capture Mode Operation Example Figure 50 Express Timer Overflow in Capture Mode ...

Page 116: ...fx 512 fx 8 fx 1 Comparator 16 bit Counter T2CNTH T2CNTL 16 bit B Data Register T2BDRH T2BDRL Clear B Match T1 A Match Buffer Register B Comparator 16 bit A Data Register T2ADRH T2ADRL T2IFR INT_ACK Clear To interrupt block A Match Buffer Register A Reload Pulse Generator T2O PWM2O R T2EN 3 T2CK 2 0 2 A Match T2CC T2EN A Match T2CC T2EN T2EN T2CRH 1 ADDRESS C3H INITIAL VALUE 0000_0000B T2MS1 T2MS0...

Page 117: ... 3 7 2 M A Match 1 T2BDRH L 5 T2ADRH L PWM2O A Match 2 T2BDRH L T2ADRH L PWM2O A Match 3 T2BDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 0 Timer 2 clock Counter T2ADRH L T2 Interrupt PWM2O B Match One shot Mode T2MS 10b and Start High T2POL 0b Set T2EN 0 Clear and Start 3 7 M A Match 1 T2BDRH L 5 T2ADRH L PWM2O A Match 2 T2BDRH L T2ADRH L PWM2O A Match 3 T2BDRH L 0000H Low Level Figure 52 16 bit PPG Mo...

Page 118: ...lse Generator T2O PWM2O R EINT12 T2CNTR T2EN 3 T2CK 2 0 Clear EIPOL1 7 6 FLAG12 EIFLAG1 3 INT_ACK Clear To interrupt block 2 2 T2MS 1 0 2 T1 A Match A Match T2CC T2EN A Match T2CC T2EN NOTE T1 A Match is a pulse for the timer 2 clock source if it is selected Figure 53 16 bit Timer 2 Block Diagram 12 3 5 Register map Table 19 TIMER 2 Register Map Name Address Direction Default Description T2ADRH C5...

Page 119: ...DRL2 T2ADRL1 T2ADRL0 R W R W R W R W R W R W R W R W Initial value FFH T2ADRL 7 0 T2 A Data Low Byte NOTE Do not write 0000H in the T2ADRH T2ADRL register when PPG mode T2BDRH Timer 2 B Data High Register C7H 7 6 5 4 3 2 1 0 T2BDRH7 T2BDRH6 T2BDRH5 T2BDRH4 T2BDRH3 T2BDRH2 T2BDRH1 T2BDRH0 R W R W R W R W R W R W R W R W Initial value FFH T2BDRH 7 0 T2 B Data High Byte T2BDRL Timer 2 B Data Low Regi...

Page 120: ...er 2ControlLow Register C2H 7 6 5 4 3 2 1 0 T2CK2 T2CK1 T2CK0 T2IFR T2POL T2CNTR R W R W R W R W R W R W Initial value 00H T2CK 2 0 Select Timer 2 clock source fx is main system clock frequency T2CK2 T2CK1 T2CK0 Description 0 0 0 fx 512 0 0 1 fx 128 0 1 0 fx 32 0 1 1 fx 8 1 0 0 fx 4 1 0 1 fx 2 1 1 0 fx 1 1 1 1 T1 A Match T2IFR When T2 Match Interrupt occurs this bit becomes 1 For clearing bit writ...

Page 121: ...ion timer 3 outputs PWM waveform through PWM3O port in the PPG mode Table 20 TIMER 3 Operating Modes T3EN P0FSRH 1 0 T3MS 1 0 T3CK 2 0 Timer 3 1 11 00 XXX 16 Bit Timer Counter Mode 1 00 01 XXX 16 Bit Capture Mode 1 11 10 XXX 16 Bit PPG Mode one shot mode 1 11 11 XXX 16 Bit PPG Mode repeat mode 12 4 1 16 bit timer counter mode 16 bit timer counter mode is selected by control registers and the 16 bi...

Page 122: ...NTL Clear Edge Detector T3ECE EC3 Comparator 16 bit A Data Register T3ADRH T3ADRL T3IFR INT_ACK Clear To interrupt block A Match Buffer Register A A Match T3CC Reload Pulse Generator T3O R T3EN 2 T3MS1 T3MS0 T3CC 0 0 X T3CK2 T3CRL X ADDRESS 1001H INITIAL VALUE 0000_0000B T3CK1 T3CK0 T3IFR T3POL T3ECE T3CNTR X X X X X X T3EN 3 T3CK 2 0 PWM3O Figure 54 16 bit Timer Counter Mode of Timer 3 Figure 55 ...

Page 123: ...e result is loaded into T3BDRH T3BDRL According to EIPOL0L registers setting the external interrupt EINT3 function is selected EINT3 pin must be set as an input port A Match T3CC T3EN P r e s c a l e r fx M U X fx 2 fx 4 fx 64 fx 512 fx 2048 fx 8 fx 1 16 bit Counter T3CNTH T3CNTL 16 bit B Data Register T3BDRH T3BDRL Clear Edge Detector T3ECE EC3 Comparator 16 bit A Data Register T3ADRH T3ADRL T3IF...

Page 124: ...12 Timer 0 1 2 3 4 5 A96G140 A96G148 A96A148 User s manual 124 Figure 57 16 bit Capture Mode Operation Example Figure 58 Express Timer Overflow in Capture Mode ...

Page 125: ...r fx M U X fx 2 fx 4 fx 64 fx 512 fx 2048 fx 8 fx 1 Comparator 16 bit Counter T3CNTH T3CNTL 16 bit B Data Register T3BDRH T3BDRL Clear B Match Edge Detector T3ECE EC3 Buffer Register B Comparator 16 bit A Data Register T3ADRH T3ADRL T3IFR INT_ACK Clear To interrupt block A Match Buffer Register A Reload Pulse Generator T3O R T3EN 2 T3EN T3CRH 1 ADDRESS 1000H INITIAL VALUE 0000_0000B T3MS1 T3MS0 T3...

Page 126: ... 3 7 2 M A Match 1 T3BDRH L 5 T3ADRH L PWM3O A Match 2 T3BDRH L T3ADRH L PWM3O A Match 3 T3BDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 0 Timer 3 clock Counter T3ADRH L T3 Interrupt PWM3O B Match One shot Mode T3MS 10b and Start High T3POL 0b Set T3EN 0 Clear and Start 3 7 M A Match 1 T3BDRH L 5 T3ADRH L PWM3O A Match 2 T3BDRH L T3ADRH L PWM3O A Match 3 T3BDRH L 0000H Low Level Figure 60 16 bit PPG Mo...

Page 127: ...A96G140 A96G148 A96A148 User s manual 12 Timer 0 1 2 3 4 5 127 ...

Page 128: ...ister A Reload Pulse Generator T3O R EINT3 T3CNTR T3EN Clear EIPOL0L 7 6 FLAG3 EIFLAG0 3 INT_ACK Clear To interrupt block 2 2 T3MS 1 0 2 Edge Detector T3ECE EC3 To Timer 4 block A Match T3CC T3EN A Match T3CC T3EN 3 T3CK 2 0 PWM3O Figure 61 16 bit Timer 3 Block Diagram 12 4 5 Register map Table 21 TIMER 3 Register Map Name Address Direction Default Description T3ADRH 1002H R W FFH Timer 3 A Data H...

Page 129: ...L2 T3ADRL1 T3ADRL0 R W R W R W R W R W R W R W R W Initial value FFH T3ADRL 7 0 T3 A Data Low Byte NOTE Do not write 0000H in the T3ADRH T3ADRL register when PPG mode T3BDRH Timer 3 B Data High Register 1004H 7 6 5 4 3 2 1 0 T3BDRH7 T3BDRH6 T3BDRH5 T3BDRH4 T3BDRH3 T3BDRH2 T3BDRH1 T3BDRH0 R W R W R W R W R W R W R W R W Initial value FFH T3BDRH 7 0 T3 B Data High Byte T3BDRL Timer 3 B Data Low Regi...

Page 130: ...0 Timer 3 disable 1 Timer 3 enable Counter clear and start T3MS 1 0 Control Timer 3 Operation Mode T3MS1 T3MS0 Description 0 0 Timer counter mode T3O toggle at A match 0 1 Capture mode The A match interrupt can occur 1 0 PPG one shot mode PWM3O 1 1 PPG repeat mode PWM3O T3CC Clear Timer 3 Counter 0 No effect 1 Clear the Timer 3 counter When write automatically cleared 0 after being cleared counter...

Page 131: ...eration 1 T3 Interrupt generation T3POL T3O PWM3O Polarity Selection 0 Start High T3O PWM3O is low level at disable 1 Start Low T3O PWM3O is high level at disable T3ECE Timer 3 External Clock Edge Selection 0 External clock falling edge 1 External clock rising edge T3CNTR Timer 3 Counter Read Control 0 No effect 1 Load the counter value to the B data register When write automatically cleared 0 aft...

Page 132: ...ting Modes T4EN P0FSRH 3 2 T4MS 1 0 T4CK 2 0 Timer 4 1 11 00 XXX 16 Bit Timer Counter Mode 1 00 01 XXX 16 Bit Capture Mode 1 11 10 XXX 16 Bit PPG Mode one shot mode 1 11 11 XXX 16 Bit PPG Mode repeat mode 12 5 1 16 bit timer counter mode 16 bit timer counter mode is selected by control registers and the 16 bit timer counter has counter registers and data registers as shown in figure 60 The counter...

Page 133: ...W Clear To interrupt block A Match Buffer Register A Reload Pulse Generator T4O R T4EN 3 T4CK 2 0 2 A Match T4CC T4EN T4EN T4CRH 1 ADDRESS 1008H INITIAL VALUE 0000_0000B T4MS1 T4MS0 T4CC 0 0 X T4CK2 T4CRL X ADDRESS 1009H INITIAL VALUE 0000_0000B T4CK1 T4CK0 T4IFR T4POL T4CNTR X X X X X PWM4O NOTE T3 A Match is a pulse for the timer 4 clock source if it is selected Figure 62 16 bit Timer Counter Mo...

Page 134: ... timer 4 output T4O waveform is not available According to EIPOL0L registers setting the external interrupt EINT4 function is selected EINT4 pin must be set as an input port A Match T4CC T4EN P r e s c a l e r fx M U X fx 2 fx 4 fx 32 fx 128 fx 512 fx 8 fx 1 16 bit Counter T4CNTH T4CNTL 16 bit B Data Register T4BDRH T4BDRL Clear T1 A Match Comparator 16 bit A Data Register T4ADRH T4ADRL T4IFR S W ...

Page 135: ...A96G140 A96G148 A96A148 User s manual 12 Timer 0 1 2 3 4 5 135 Figure 65 16 bit Capture Mode Operation Example Figure 66 Express Timer Overflow in Capture Mode ...

Page 136: ...fx 512 fx 8 fx 1 Comparator 16 bit Counter T4CNTH T4CNTL 16 bit B Data Register T4BDRH T4BDRL Clear B Match T3 A Match Buffer Register B Comparator 16 bit A Data Register T4ADRH T4ADRL T4IFR S W Clear To interrupt block A Match Buffer Register A Reload Pulse Generator T4O R T4EN 3 T4CK 2 0 2 A Match T4CC T4EN A Match T4CC T4EN T4EN T4CRH 1 ADDRESS 1008H INITIAL VALUE 0000_0000B T4MS1 T4MS0 T4CC 1 ...

Page 137: ... 3 7 2 M A Match 1 T4BDRH L 5 T4ADRH L PWM4O A Match 2 T4BDRH L T4ADRH L PWM4O A Match 3 T4BDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 0 Timer 4 clock Counter T4ADRH L T4 Interrupt PWM4O B Match One shot Mode T4MS 10b and Start High T4POL 0b Set T4EN 0 Clear and Start 3 7 M A Match 1 T4BDRH L 5 T4ADRH L PWM4O A Match 2 T4BDRH L T4ADRH L PWM4O A Match 3 T4BDRH L 0000H Low Level Figure 68 16 bit PPG Mo...

Page 138: ...erator T4O R EINT4 T4CNTR T4EN 3 T4CK 2 0 Clear EIPOL0H 1 0 FLAG4 EIFLAG0 4 INT_ACK Clear To interrupt block 2 2 T4MS 1 0 2 T3 A Match A Match T4CC T4EN A Match T4CC T4EN PWM4O NOTE T3 A Match is a pulse for the timer 4 clock source if it is selected Figure 69 16 bit Timer 4 Block Diagram 12 5 5 Register map Table 23 TIMER 4 Register Map Name Address Direction Default Description T4ADRH 100AH R W ...

Page 139: ...DRL2 T4ADRL1 T4ADRL0 R W R W R W R W R W R W R W R W Initial value FFH T4ADRL 7 0 T4 A Data Low Byte NOTE Do not write 0000H in the T4ADRH T4ADRL register when PPG mode T4BDRH Timer 4 B Data High Register 100CH 7 6 5 4 3 2 1 0 T4BDRH7 T4BDRH6 T4BDRH5 T4BDRH4 T4BDRH3 T4BDRH2 T4BDRH1 T4BDRH0 R W R W R W R W R W R W R W R W Initial value FFH T4BDRH 7 0 T4 B Data High Byte T4BDRL Timer 4 B Data Low Re...

Page 140: ...ounter T4CRL Timer 4 Control Low Register 1009H 7 6 5 4 3 2 1 0 T4CK2 T4CK1 T4CK0 T4IFR T4POL T4CNTR R W R W R W R W R W R W Initial value 00H T4CK 2 0 Select Timer 4 clock source fx is main system clock frequency T4CK2 T4CK1 T4CK0 Description 0 0 0 fx 512 0 0 1 fx 128 0 1 0 fx 32 0 1 1 fx 8 1 0 0 fx 4 1 0 1 fx 2 1 1 0 fx 1 1 1 1 T3 A Match T4IFR When T4 Match Interrupt occurs this bit becomes 1 F...

Page 141: ...henever counter value is equal to T5ADRH L T5O port toggles In addition the TIMER 5 outputs PWM waveform to PWM5O port in the PPG mode Table 24 TIMER 5 Operating Modes T5EN P0FSRH 5 4 T5MS 1 0 T5CK 2 0 Timer 5 1 11 00 XXX 16 Bit Timer Counter Mode 1 00 01 XXX 16 Bit Capture Mode 1 11 10 XXX 16 Bit PPG Mode one shot mode 1 11 11 XXX 16 Bit PPG Mode repeat mode 12 6 1 16 bit timer counter mode 16 bi...

Page 142: ...ta Register T5ADRH T5ADRL T5IFR S W Clear To interrupt block A Match Buffer Register A Reload Pulse Generator T5O R T5EN 3 T5CK 2 0 2 A Match T5CC T5EN T5EN T5CRH 1 ADDRESS 1010H INITIAL VALUE 0000_0000B T5MS1 T5MS0 T5CC 0 0 X T5CK2 T5CRL X ADDRESS 1011H INITIAL VALUE 0000_0000B T5CK1 T5CK0 T5IFR T5POL T5CNTR X X X X X PWM5O Figure 70 16 bit Timer Counter Mode of Timer 5 Figure 71 16 bit Timer Cou...

Page 143: ...5BDRH T5BDRL In the timer 5 capture mode timer 5 output T5O waveform is not available According to EIPOL0H registers setting the external interrupt EINT5 function is selected EINT5 pin must be set as an input port A Match T5CC T5EN P r e s c a l e r fx M U X fx 2 fx 4 fx 32 fx 128 fx 512 fx 8 fx 1 16 bit Counter T5CNTH T5CNTL 16 bit B Data Register T5BDRH T5BDRL Clear HIRC Comparator 16 bit A Data...

Page 144: ...G148 A96A148 User s manual 144 Figure 73 16 bit Capture Mode Operation Example Figure 74 Express Timer Overflow in Capture Mode 12 6 3 16 bit PPG mode TIMER 5 has a PPG Programmable Pulse Generation function In PPG mode T5O PWM5O pin ...

Page 145: ...x 1 Comparator 16 bit Counter T5CNTH T5CNTL 16 bit B Data Register T5BDRH T5BDRL Clear B Match HIRC Buffer Register B Comparator 16 bit A Data Register T5ADRH T5ADRL T5IFR S W Clear To interrupt block A Match Buffer Register A Reload Pulse Generator T5O R T5EN 3 T5CK 2 0 2 A Match T5CC T5EN A Match T5CC T5EN T5EN T5CRH 1 ADDRESS 1010H INITIAL VALUE 0000_0000B T5MS1 T5MS0 T5CC 1 1 X T5CK2 T5CRL X A...

Page 146: ... 3 7 2 M A Match 1 T5BDRH L 5 T5ADRH L PWM5O A Match 2 T5BDRH L T5ADRH L PWM5O A Match 3 T5BDRH L 0000H Low Level X 1 2 4 5 6 8 M 1 0 Timer 5 clock Counter T5ADRH L T5 Interrupt PWM5O B Match One shot Mode T5MS 10b and Start High T5POL 0b Set T5EN 0 Clear and Start 3 7 M A Match 1 T5BDRH L 5 T5ADRH L PWM5O A Match 2 T5BDRH L T5ADRH L PWM5O A Match 3 T5BDRH L 0000H Low Level Figure 76 16 bit PPG Mo...

Page 147: ...Match Buffer Register A Reload Pulse Generator T5O R EINT5 T5CNTR T5EN 3 T5CK 2 0 Clear EIPOL0H 3 2 FLAG5 EIFLAG0 5 INT_ACK Clear To interrupt block 2 2 T5MS 1 0 2 HIRC A Match T5CC T5EN A Match T5CC T5EN PWM5O Figure 77 16 bit Timer 5 Block Diagram 12 6 5 Register map Table 25 TIMER 5 Register Map Name Address Direction Default Description T5ADRH 1012H R W FFH Timer 5 A Data High Register T5ADRL ...

Page 148: ...DRL2 T5ADRL1 T5ADRL0 R W R W R W R W R W R W R W R W Initial value FFH T5ADRL 7 0 T5 A Data Low Byte NOTE Do not write 0000H in the T5ADRH T5ADRL register when PPG mode T5BDRH Timer 5 B Data High Register 1014H 7 6 5 4 3 2 1 0 T5BDRH7 T5BDRH6 T5BDRH5 T5BDRH4 T5BDRH3 T5BDRH2 T5BDRH1 T5BDRH0 R W R W R W R W R W R W R W R W Initial value FFH T5BDRH 7 0 T5 B Data High Byte T5BDRL Timer 5 B Data Low Re...

Page 149: ...er T5CRL Timer 5 Control Low Register 1011H 7 6 5 4 3 2 1 0 T5CK2 T5CK1 T5CK0 T5IFR T5POL T5CNTR R W R W R W R W R W R W Initial value 00H T5CK 2 0 Select Timer 5 clock source fx is main system clock frequency T4CK2 T4CK1 T4CK0 Description 0 0 0 fx 512 0 0 1 fx 128 0 1 0 fx 32 0 1 1 fx 8 1 0 0 fx 4 1 0 1 fx 2 1 1 0 fx 1 1 1 1 HSIRC Direct 32MHz T5IFR When T5 Match Interrupt occurs this bit becomes...

Page 150: ...ce clock divided by prescaler Table 26 Buzzer Frequency at 8MHz BUZDR 7 0 Buzzer Frequency KHz BUZCR 2 1 00 BUZCR 2 1 01 BUZCR 2 1 10 BUZCR 2 1 11 0000_0000 125KHz 62 5KHz 31 25KHz 15 625KHz 0000_0001 62 5KHz 31 25KHz 15 625KHz 7 812KHz 1111_1101 492 126Hz 246 063Hz 123 031Hz 61 515Hz 1111_1110 490 196Hz 245 098Hz 122 549Hz 61 274Hz 1111_1111 488 281Hz 244 141Hz 122 07Hz 61 035Hz 13 1 Buzzer drive...

Page 151: ...6 BUZDR5 BUZDR4 BUZDR3 BUZDR2 BUZDR1 BUZDR0 R W R W R W R W R W R W R W R W Initial value FFH BUZDR 7 0 This bits control the Buzzer frequency Its resolution is 00H FFH BUZCR Buzzer Control Register 97H 7 6 5 4 3 2 1 0 BUCK1 BUCK0 BUZEN R W R W R W Initial value 00H BUCK 1 0 Buzzer Driver Source Clock Selection BUCK1 BUCK0 Description 0 0 fx 32 0 1 fx 64 1 0 fx 128 1 1 fx 256 BUZEN Buzzer Driver O...

Page 152: ...e conversion is completed the result is loaded into ADCDRH and ADCDRL A D conversion status bit AFLAG is set to 1 and A D interrupt is set During the A D conversion AFLAG bit is read as 0 14 1 Conversion timing A D conversion process requires 4 steps 4 clock edges to convert each bit and 12 clocks to set up A D conversion Therefore total of 58 clocks are required to complete a 12 bit conversion Fo...

Page 153: ...N0 Reference Voltage AVREF AVSS AN1 AN2 AN14 AN15 ADCIFR AFLAG INT_ACK Clear Clear To interrupt block MUX VDD Start M U X T3 A match signal EXTINT0 7 REFSEL TRIG 2 0 3 ADST T1 A match signal EXTINT8 Figure 79 12 bit ADC Block Diagram Figure 80 A D Analog Input Pin with a Capacitor AVREF Analog Power Input 22uF Figure 81 A D Power AVREF Pin with a Capacitor 0 100Ω 0 1000pF ANx Analog Input ...

Page 154: ...H4 ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4 ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 Align bit set 1 ADCDRH3 ADCDRH2 ADCDRH1 ADCDRH0 ADCDRL7 ADCDRL6 ADCDRL5 ADCDRL4 ADCDRL3 ADCDRL2 ADCDRL1 ADCDRL0 ADCO11 ADCO10 ADCO9 ADCO8 ADCO7 ADCO6 ADCO5 ADCO4 ADCO3 ADCO2 ADCO1 ADCO0 ADCDRL 7 0 ADCDRL 3 0 ADCDRL 7 4 bits are 0 ADCDRH 7 0 ADCDRL 7 4 ADCDRL ...

Page 155: ... R xxH A D Converter Data Low Register ADCCRH 9DH R W 01H A D Converter Control High Register ADCCRL 9CH R W 00H A D Converter Control Low Register 14 5 Register description ADCDRH A D Converter Data High Register 9FH 7 6 5 4 3 2 1 0 ADDM11 ADDM10 ADDM9 ADDM8 ADDM7 ADDL11 ADDM6 ADDL10 ADDM5 ADDL9 ADDM4 ADDL8 R R R R R R R R Initial value xxH ADDM 11 4 MSB align A D Converter High Data 8 bit ADDL 1...

Page 156: ...omes 1 For clearing bit write 0 to this bit or auto clear by INT_ACK signal Writing 1 has no effect 0 ADC Interrupt no generation 1 ADC Interrupt generation IREF Select internal voltage reference 0 External input signal source select 1 Test only TRIG 2 0 A D Trigger Signal Selection TRIG2 TRIG1 TRIG0 Description 0 0 0 ADST 0 0 1 Timer 1 A match signal 0 1 0 Timer 3 A match signal 0 1 1 EXTINT0 7 1...

Page 157: ...effect 1 ADC Conversion Start and auto clear REFSEL A D Converter Reference Selection 0 Internal Reference VDD 1 External Reference AVREF AFLAG A D Converter Operation State This bit is cleared to 0 when the STBY bit is set to 0 or when the CPU is at STOP mode 0 During A D Conversion 1 A D Conversion finished ADSEL 3 0 A D Converter input selection ADSEL3 ADSEL2 ADSEL1 ADSEL0 Description 0 0 0 0 A...

Page 158: ...de USART SPI mode I2C mode 15 1 USIn UART mode Universal synchronous and asynchronous serial receiver and transmitter USART are highly flexible serial communication devices Main features are listed below Full Duplex Operation Independent Serial Receive and Transmit Registers Asynchronous or Synchronous Operation Baud Rate Generator Supports Serial Frames with 5 6 7 8 or 9 Data bits and 1 or 2 Stop...

Page 159: ...he same frame formats as the transmitter and can detect frame error data overrun and parity errors 15 2 USIn UART block diagram RXDn Rx Control Clock Recovery Receive Shift Register RXSR Data Recovery DORn PEn FEn Checker USInDR 0 USInRX8 0 Rx USInDR 1 USInRX8 1 Rx TXDn Tx Control Stop bit Generator Parity Generator Transmit Shift Register TXSR USInDR USInTX8 Tx USInP 1 0 M U X LOOPSn TXCn TXCIEn ...

Page 160: ...CR1 register selects one from asynchronous operation and synchronous operation Asynchronous double speed mode is controlled by the DBLSn bit in the USInCR2 register The MASTERn bit in USInCR3 register controls whether the clock source is internal master mode output pin or external slave mode input pin The SCKn pin is active only when the USIn operates in synchronous or SPI mode Table 29 shows the ...

Page 161: ...ave or clock output master Data sampling and transmitter are issued on the different edge of SCKn clock respectively For example if data input on RXDn MISOn in SPI mode pin is sampled on the rising edge of SCKn clock data output on TXDn MOSIn in SPI mode pin is altered on the falling edge CPOLn bit in USInCR1 register selects which SCKn clock edge will be used both for data sampling and data chang...

Page 162: ...re 85 shows a possible combination of the frame formats Bits inside brackets are optional Figure 87 Frame Formats USIn 1 data frame consists of the following bits Idle No communication on communication line TXDn RXDn St Start bit Low Dn Data bits 0 8 Parity bit Even parity odd parity no parity Stop bit s 1 bit or 2 bits A frame format used by the UART is determined by the USInS 2 0 USInPM 1 0 bits...

Page 163: ...smitted When the shift register is loaded with new data it will transfer one complete frame according to the settings of control registers If the 9 bit characters are used in asynchronous or synchronous operation mode the ninth bit must be written to the USInTX8 bit in USInCR3 register before it is loaded to the transmit buffer USInDR register 15 8 2 USIn UART transmitter flag and interrupt The US...

Page 164: ...ynchronous or SPI operation mode the SCKn pin is used as transfer clock input so it should be selected to do SCKn function by P4FSR 5 4 and P2FSR 3 2 In SPI operation mode the SSn input pin in slave mode or can be configured as SSn output pin in master mode This can be done by setting USInSSEN bit in USInCR3 register 15 9 1 USIn UART receiver RX data When UART is in synchronous or asynchronous ope...

Page 165: ...d as 0 This flag can be used for detecting out of sync conditions between data frames The data overrun DORn flag indicates data loss due to a receive buffer full condition DORn occurs when the receive buffer is full and another new data is presented in the receive shift register which are to be stored into the receive buffer After the DORn flag is set all the incoming data are lost To avoid data l...

Page 166: ... start bit is detected and the internally generated clock is synchronized to the incoming data frame And the data recovery can begin The synchronization process is repeated for each start bit As described above when the receiver clock is synchronized to the start bit the data recovery can begin Data recovery process is almost same to the clock recovery process The data recovery logic samples 16 ti...

Page 167: ...SIn 15 10 USIn SPI mode The USIn can be set to operate in industrial standard SPI compliant mode The SPI mode has the following features Full duplex three wire synchronous data transfer Master and slave operation Supports all four SPIn modes of operation mode 0 1 2 and 3 Selectable LSB first or MSB first data transfer Double buffered transmit and receive Programmable transmit bit rate When SPI mod...

Page 168: ... relationships between the clock and data Note that CPHAn and CPOLn bits in USInCR1 register have different meanings according to the USInMS 1 0 bits which decides the operating mode of USIn Table 29 shows four combinations of CPOLn and CPHAn for SPI mode 0 1 2 and 3 Table 30 CPOLn Functionality SPI Mode CPOLn CPHAn Leading Edge Trailing Edge 0 0 0 Sample Rising Setup Falling 1 0 1 Setup Rising Sa...

Page 169: ...SCKn edge The first SCKn edge shifts the first bit of data from the shifter onto the MOSIn output of the master and the MISOn output of the slave The next SCKn edge causes both the master and slave to sample the data bit value on their MISOn and MOSIn inputs respectively At the third SCKn edge the USIn shifts the second data bit value out to the MOSIn and MISOn output of the master and slave respe...

Page 170: ...d Rate Generator USInBD TXEn SCLK fx System clock MISOn MOSIn M U X MASTERn D E P FXCHn SCKn SCK Control MASTERn RXEn To interrupt block M U X Edge Detector And Controller SSn SS Control CPHAn CPOLn ORDn MSB LSB 1st USInDR 1 Rx USInSSEN Figure 93 USIn SPI Block Diagram n 0 and 1 15 13 USIn I2C mode The USIn can be set to operate in industrial standard serial communication protocols mode The I2C mo...

Page 171: ... SCLn SDAn lines that it will use the bus A STOP P condition is generated by the master to release the bus lines so that other devices can use it A high to low transition on the SDAn line while SCLn is high defines a START S condition A low to high transition on the SDAn line while SCLn is high defines a STOP P condition START and STOP conditions are always generated by the master The bus is consi...

Page 172: ...ledge related clock pulse is generated by the master The transmitter releases the SDAn line HIGH during the acknowledge clock pulse The receiver must pull down the SDAn line during the acknowledge clock pulse so that it remains stable LOW during the HIGH period of this clock pulse When a slave is addressed by a master Address Packet and if it is unable to receive or transmit because it s performin...

Page 173: ...t state until the clock HIGH state is reached However the LOW to HIGH transition of this clock may not change the state of the SCLn line if another clock is still within its LOW period In this way a synchronized SCLn clock is generated with its LOW period determined by the device with the longest clock LOW period and its HIGH period determined by the one with the shortest clock HIGH period A maste...

Page 174: ...ter is set it is cleared by writing any value to USInST2 When I2C interrupt occurs the SCLn line is hold LOW until writing any value to USInST2 When the IICnIFR flag is set the USInST2 contains a value indicating the current state of the I2C bus According to the value in USInST2 software can decide what to do next I2C can operate in 4 modes by configuring master slave transmitter receiver The oper...

Page 175: ...7 bit address and 1 bit transfer direction is transmitted to target slave device the master can know whether the slave acknowledged or not in the 9th high period of SCLn If the master gains bus mastership I2C generates GCALL interrupt regardless of the reception of ACK from the slave device When I2C loses bus mastership during arbitration process the MLOSTn bit in USInST2 is set and I2C waits in i...

Page 176: ...ely I2C generates TENDn interrupt I2C can choose one of the following cases regardless of the reception of ACK signal from slave Case 1 Master receives ACK signal from slave so continues data transfer because slave can receive more data from master In this case load data to transmit to USInDR Case 2 Master stops data transfer even if it receives ACK signal from slave In this case set the STOPCn bi...

Page 177: ...When 7 bit address and 1 bit transfer direction is transmitted to target slave device the master can know whether the slave acknowledged or not in the 9th high period of SCLn If the master gains bus mastership I2C generates GCALL interrupt regardless of the reception of ACK from the slave device When I2C loses bus mastership during arbitration process the MLOSTn bit in USInST2 is set and I2C waits...

Page 178: ...e To do this set ACKnEN bit in USInCR4 to ACKnowledge the next data to be received Case 2 Master wants to terminate data transfer when it receives next data by not generating ACK signal This can be done by clearing ACKnEN bit in USInCR4 Case 3 Because no ACK signal is detected master terminates data transfer In this case set the STOPCn bit in USInCR4 Case 4 No ACK signal is detected and master tra...

Page 179: ...d I2C generates SSELn interrupt and the SCLn line is held LOW Note that even if the address equals to USInSLA 6 0 bits when the ACKnEN bit is disabled I2C enters idle state When SSELn interrupt occurs load transmit data to USInDR and write arbitrary value to USInST2 to release SCLn line 5 1 Byte of data is being transmitted 6 In this step I2C generates TENDn interrupt and holds the SCLn line LOW r...

Page 180: ...to SLAn bits and the ACKnEN bit is enabled I2C generates SSELn interrupt and the SCLn line is held LOW Note that even if the address equals to SLAn bits when the ACKnEN bit is disabled I2C enters idle state When SSELn interrupt occurs and I2C is ready to receive data write arbitrary value to USInST2 to release SCLn line 5 Byte of data is being received 6 In this step I2C generates TENDn interrupt ...

Page 181: ...n block is an I2C mode and the corresponding port is a sub function for SCLn SDAn pin The SCLn SDAn pins are automatically set to the N channel open drain outputs and the input latch is read in the case of reading the pins The corresponding pull up resistor is determined by the control register Figure 100 USIn I2C Block Diagram 15 21 Register map Table 31 USI Register Map Name Address Direction De...

Page 182: ...Control Register 2 USI1CR3 EBH R W 00H USI1 Control Register 3 USI1CR4 ECH R W 00H USI1 Control Register 4 USI1ST1 F1H R W 80H USI1 Status Register 1 USI1ST2 F2H R 00H USI1 Status Register 2 15 22 USIn register description USInBD USIn Baud Rate Generation Register For UART and SPI mode E3H F3H n 0 1 7 6 5 4 3 2 1 0 USInBD7 USInBD6 USInBD5 USInBD4 USInBD3 USInBD2 USInBD1 USInBD0 R W R W R W R W R W...

Page 183: ...al value 01H USInSDHR 7 0 The register is used to control SDAn output timing from the falling edge of SCI in I2C mode NOTES 1 That SDAn is changed after tSCLK X USInSDHR 2 in master SDAn change in the middle of SCLn 2 In slave mode configure this register regarding the frequency of SCLn from master 3 The SDAn is changed after tSCLK X USInSDHR 2 in master mode So to insure operation in slave mode t...

Page 184: ...k is SCLK the system clock and the period is calculated by the formula tSCLK X 4 X USInSCLR 2 where tSCLK is the period of SCLK USInSAR USIn Slave Address Register For I2C mode DDH EDH n 0 1 7 6 5 4 3 2 1 0 USInSLA6 USInSLA5 USInSLA4 USInSLA3 USInSLA2 USInSLA1 USInSLA0 USInGCE R W R W R W R W R W R W R W R W Initial value 00H USInSLA 6 0 These bits configure the slave address of I2C when it operat...

Page 185: ...ength of data bits in frame USInS2 USInS1 USInS0 Data Length 0 0 0 5 bit 0 0 1 6 bit 0 1 0 7 bit 0 1 1 8 bit 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 9 bit ORDn This bit in the same bit position with USInS1 The MSB of the data byte is transmitted first when set to 1 and the LSB when set to 0 only SPI mode 0 LSB first 1 MSB first CPHAn This bit is in the same bit position with USInS0 This...

Page 186: ...use polling 1 When RXCn is set request an interrupt WAKEIEn Interrupt enable bit for asynchronous wake in STOP mode When device is in stop mode if RXDn goes to low level an interrupt can be requested to wake up system only UART mode At that time the DRIEn bit and USInST1 register value should be set to 0b and 00H respectively 0 Interrupt from Wake is inhibited 1 When WAKEn is set request an interr...

Page 187: ...ACK is free running while UART is enabled in synchronous master mode 1 ACK is active while any frame is on transferring USInSSEN This bit controls the SSn pin operation only SPI mode 0 Disable 1 Enable FXCHn SPI port function exchange control bit only SPI mode 0 No effect 1 Exchange MOSIn and MISOn function USInSB Selects the length of stop bit in asynchronous or synchronous mode of operation 0 1 ...

Page 188: ... bit for I2C mode 0 Interrupt from I2C is inhibited use polling 1 Enable interrupt for I2C ACKnEN Controls ACK signal Generation at ninth SCLn period 0 No ACK signal is generated SDAn 1 1 ACK signal is generated SDAn 0 NOTE ACK signal is output SDA 0 for the following 3 cases When received address packet equals to USInSLA bits in USInSAR When received address packet equals to value 0x00 with GCALL...

Page 189: ...generate an RXCn interrupt 0 There is no data unread in the receive buffer 1 There are more than 1 data in the receive buffer WAKEn This flag is set when the RXDn pin is detected low while the CPU is in STOP mode This flag can be used to generate a WAKEn interrupt This bit is set only when in asynchronous mode of operation This bit should be cleared by program software only UART mode 0 No WAKE int...

Page 190: ...TOP condition is detected 0 No STOP condition is detected 1 STOP condition is detected SSELn NOTE This bit is set when I2C is addressed by other master 0 I2C is not selected as a slave 1 I2C is addressed by other master and acts as a slave MLOSTn NOTE This bit represents the result of bus arbitration in master mode 0 I2C maintains bus mastership 1 I2C maintains bus mastership during arbitration pr...

Page 191: ...00 25 0 2 47 0 0 51 0 2 4800 12 0 2 23 0 0 25 0 2 9600 6 7 0 11 0 0 12 0 2 14 4k 3 8 5 7 0 0 8 3 5 19 2k 2 8 5 5 0 0 6 7 0 28 8k 1 8 5 3 0 0 3 8 5 38 4k 1 18 6 2 0 0 2 8 5 57 6k 1 25 0 1 8 5 76 8k 1 0 0 1 18 6 115 2k 230 4k 2400 25 0 2 47 0 0 51 0 2 4800 12 0 2 23 0 0 25 0 2 9600 6 7 0 11 0 0 12 0 2 14 4k 3 8 5 7 0 0 8 3 5 19 2k 2 8 5 5 0 0 6 7 0 28 8k 1 8 5 3 0 0 3 8 5 38 4k 1 18 6 2 0 0 2 8 5 57...

Page 192: ...r Frequencies Baud rate bps fx 8 00MHz fx 11 0592MHz USI0BD USI1BD Error USI0BD USI1BD Error 2400 207 0 2 4800 103 0 2 143 0 0 9600 51 0 2 71 0 0 14 4k 34 0 8 47 0 0 19 2k 25 0 2 35 0 0 28 8k 16 2 1 23 0 0 38 4k 12 0 2 17 0 0 57 6k 8 3 5 11 0 0 76 8k 6 7 0 8 0 0 115 2k 3 8 5 5 0 0 230 4k 1 8 5 2 0 0 250k 1 0 0 2 7 8 0 5M 1M ...

Page 193: ...a Register Empty and RX Complete Double Speed Asynchronous Communication Mode USART2 has three main parts such as a Clock Generator Transmitter and Receiver Clock Generation logic consists of a synchronization logic for external clock input used by synchronous or SPI slave operation and a baud rate generator for asynchronous or master synchronous or SPI operation Transmitter consists of a single w...

Page 194: ...p bit Generator UDATA Tx SS2 SS Control RXC TXC UPM1 UPM0 USIZE2 USIZE1 USIZE0 UCPOL UCTRL1 ADDRESS CBH INITIAL VALUE 0000_0000B UDRIE TXCIE RXCIE TXE RXE U2X UCTRL2 ADDRESS CCH INITIAL VALUE 0000_0000B LOOPS SPISS USBS TX8 RX8 UCTRL3 ADDRESS CDH INITIAL VALUE 0000_ 000B UDRE TXC RXC WAKE DOR FE PE USTAT ADDRESS CFH INITIAL VALUE 1000_0000B SCLK Rx Interrupt Tx Interrupt I n t e r n a l B u s L i ...

Page 195: ... is controlled by the U2X bit in the UCTRL2 register The MASTER bit in UCTRL2 register controls whether the clock source is internal Master mode output port or external Slave mode input port The XCK pin is only active when the USART2 operates in Synchronous or SPI mode Figure 102 Clock Generation Block Diagram Table 33 contains equations for calculating the baud rate in bps Table 34 Equations for ...

Page 196: ...LK is frequency of main system clock SCLK 16 4 Synchronous mode operation When synchronous mode or SPI mode is used the XCK pin will be used as either clock input slave or clock output master The dependency between a clock edge and data sampling or data change is the same The basic principle is that data input on RXD2 MISO2 in SPI mode pin is sampled at the opposite XCK clock edge at the edge in t...

Page 197: ...s before the stop bits A high to low transition on data pin is considered as start bit When a complete frame is transmitted it can be directly followed by a new frame or the communication line can be set to an idle state The idle means high state of data pin The next figure shows the possible combinations of the frame formats Bits inside brackets are optional Figure 104 A Frame Format Single data ...

Page 198: ... 7 1 Sending Tx data A data transmission is initiated by loading a transmit buffer UDATA register I O location with data to be transmitted The data written in the transmit buffer is moved to a shift register when the shift register is ready to send a new frame The shift register is loaded with new data if it is in idle state or immediately after the last stop bit of the previous frame is transmitt...

Page 199: ...ter is disabled the TXD2 pin is used as normal General Purpose I O GPIO or primary function pin 16 8 USART2 receiver USART2 Receiver is enabled by setting the RXE bit in the UCTRL1 register When the Receiver is enabled normal pin operation of RXD2 pin is overridden by the USART2 as the serial input pin of the Receiver Baud rate mode of operation and frame format must be set before serial reception...

Page 200: ...ived data from UDATA register read the USTAT register first which contains error flags Frame Error FE flag indicates the state of the first stop bit The FE flag is set when the stop bit was correctly detected as 1 and the FE flag is cleared when the stop bit was incorrect i e detected as 0 This flag can be used for detecting out of sync conditions between data frames Data Over Run DOR flag indicat...

Page 201: ...8 9 and 10 for Normal mode and the samples 4 5 and 6 for Double Speed mode to decide if a valid start bit is received If more than 2 samples have logical low level it is considered that a valid start bit is detected and the internally generated clock is synchronized to the incoming data frame And the data recovery can begin The synchronization process is repeated for each start bit As described ab...

Page 202: ... detection Figure 107 Stop Bit Sampling and Next Start Bit Sampling 16 9 SPI mode The USART2 can be set to operate in industrial standard SPI compliant mode The SPI mode has the following features Full duplex three wire synchronous data transfer Master or Slave operation Supports all four SPI modes of operation mode0 1 2 and 3 Selectable LSB first or MSB first data transfer Double buffered transmi...

Page 203: ...lock UCPHA selects one of two different clock phase relationships between the clock and the data Note that UCPHA and UCPOL bits in UCTRL1 register have different meanings according to the UMSEL 1 0 bits which decides the operating mode of USART2 Table 34 shows four combinations of UCPOL and UCPHA for SPI mode 0 1 2 and 3 Table 35 CPOL Functionality SPI Mode UCPOL UCPHA Leading Edge Trailing Edge 0...

Page 204: ... but the data is not defined until the first XCK edge The first XCK edge shifts the first bit of data from the shifter onto the MOSI2 output of the master and the MISO2 output of the slave The next XCK edge causes both the master and the slave to sample the data bit value on their MISO2 and MOSI2 inputs respectively At the third XCK edge the USART2 shifts the second data bit value out to the MOSI2...

Page 205: ... sysclk 16MHz Baud rate 115 200 bps Asynchronous Normal Mode U2X 0 Baud rate sysclk 16 x UBAUD 1 Calculated UBAUD 1000000 Target Baud rate 1 7 68 Error rate 0 68 UBAUD 8 Real baud rate at sysclk 16Mhz 111 111 bps 1 bit time 9us Maximum count time 9us 65536 16bit count 589 8ms USART RX Start bit Data bit Parity bit Stop bit 1 bit time 9us 111111 bps 1 Frame time parity 1 Stop 99us 111111 bps A96G14...

Page 206: ...ister UCTRL3 CDH R W 00H USART2 Control 3 Register UCTRL4 1018H R W 00H USART2 Control 4 Register USTAT CFH R 80H USART2 Status Register UBAUD FCH R W FFH USART2 Baud Rate Generation Register UDATA FDH R W 00H USART2 Data Register FPCR 1019H R W 00H USART2 Floating Point Counter Register RTOCH 101AH R 00H Receiver Time Out Counter High Register RTOCL 101BH R 00H Receiver Time Out Counter Low Regis...

Page 207: ...d 1 1 0 Reserved 1 1 1 9 bit UDORD This bit is in the same bit position with USIZE1 In SPI mode when set to one the MSB of the data byte is transmitted first When set to zero the LSB of the data byte is transmitted first 0 LSB First 1 MSB First UCPOL Selects polarity of XCK in synchronous or SPI mode 0 TXD2 change Rising Edge RXD2 change Falling Edge 1 TXD2 change Falling Edge RXD2 change Rising E...

Page 208: ...se polling 1 When RXC is set request an interrupt WAKEIE Interrupt enable bit for Asynchronous Wake in STOP mode When device is in stop mode if RXD2 goes to LOW level an interrupt can be requested to wake up system 0 Interrupt from Wake is inhibited 1 When WAKE is set request an interrupt NOTE WAKEIE must set after USARTEN setting 1 TXE Enables the transmitter unit 0 Transmitter is disabled 1 Tran...

Page 209: ...running while USART is enabled in synchronous master mode 1 XCK is active while any frame is on transferring SPISS Controls the functionality of SS2 pin in master SPI mode 0 SS2 pin is normal GPIO or other primary function 1 SS2 output to other slave device USBS Selects the length of stop bit in Asynchronous or Synchronous mode of operation 0 1 Stop bit 1 2 Stop bit TX8 The ninth bit of data frame...

Page 210: ...ut 0 Disable 1 Enable RTO_FLAG This bit is set when RTO count overflows This flag can generate an RTO interrupt Writing 0 to this bit position will clear RTO_FLAG 0 RTO count dose not overflow 1 RTO count overflow FPCREN Enable baud rate compensation 0 Disable 1 Enable AOVSSEL Select additional oversampling rates 0 Select X13 1 Select X4 AOVSEN Enable additional oversampling rates selection 0 Disa...

Page 211: ... 0 There is no data unread in the receive buffer 1 There are more than 1 data in the receive buffer WAKE This flag is set when the RX pin is detected low while the CPU is in stop mode This flag can be used to generate a WAKE interrupt This bit is set only when in asynchronous mode of operation NOTE 0 No WAKE interrupt is generated 1 WAKE interrupt is generated SOFTRST This is an internal reset and...

Page 212: ...nts of the Receive Buffer Write this register only when the UDRE flag is set In SPI or synchronous master mode write this register even if TX is not enabled to generate clock XCK FPCR USART Floating Point Register 1019H 7 6 5 4 3 2 1 0 FPCR7 FPCR6 FPCR5 FPCR4 FPCR3 FPCR2 FPCR1 FPCR0 R W R W R W R W R W R W R W R W Initial value 00H FPCR 7 0 USART Floating Point Counter 8 bit floating point counter...

Page 213: ...101AH 7 6 5 4 3 2 1 0 RTOCH7 RTOCH6 RTOCH5 RTOCH4 RTOCH3 RTOCH2 RTOCH1 RTOCH0 R W R W R W R W R W R W R W R W Initial value 00H RTOCL Receiver Time Out Counter Low Register 101BH 7 6 5 4 3 2 1 0 RTOCL7 RTOCL6 RTOCL5 RTOCL4 RTOCL3 RTOCL2 RTOCL1 RTOCL0 R W R W R W R W R W R W R W R W Initial value 00H ...

Page 214: ...3 0 2 95 0 0 191 0 0 9600 23 0 0 47 0 0 25 0 2 51 0 2 47 0 0 95 0 0 14 4K 15 0 0 31 0 0 16 2 1 34 0 8 31 0 0 63 0 0 19 2K 11 0 0 23 0 0 12 0 2 25 0 2 23 0 0 47 0 0 28 8K 7 0 0 15 0 0 8 3 5 16 2 1 15 0 0 31 0 0 38 4K 5 0 0 11 0 0 6 7 0 12 0 2 11 0 0 23 0 0 57 6K 3 0 0 7 0 0 3 8 5 8 3 5 7 0 0 15 0 0 76 8K 2 0 0 5 0 0 2 8 5 6 7 0 5 0 0 11 0 0 115 2K 1 0 0 3 0 0 1 8 5 3 8 5 3 0 0 7 0 0 230 4K 1 0 0 1 ...

Page 215: ...unter value is defined by baud rate error In the baud rate formula BAUD is presented in the integer count value For example If you want to use the 57600 baud rate fXIN 16MHz integer count value must be 16 36 value BAUD 1 16000000 16 57600 17 36 Here the accurate BAUD value is 16 36 To achieve the 0 error of baud rate floating point counter value must be 164 17 16 36 x 256 164 and BAUD value must b...

Page 216: ...6G148 A96A148 User s manual 216 Figure 111 0 Error Baud Rate Block Diagram Integer count value Integer count value 1 8bit Max floating point count value 8bit floating point counter TXD clock Generator 0 1 0 Error Baud rate ...

Page 217: ...disabled ALL CPU operations are disabled RAM Retains Retains Basic Interval Timer Operates continuously Stops can be operated with WDTRC OSC Watch Dog Timer Operates continuously Stops can be operated with WDTRC OSC Watch Timer Operates continuously Stops can be operated with sub clock Timer0 4 Operates continuously Halts only when the event counter mode is enabled timer operates normally ADC Oper...

Page 218: ...mode If using a reset because the device is initialized registers become to have reset values Figure 112 IDLE Mode Release Timing by an External Interrupt 17 3 STOP mode Power control register is set to 03H to enter into STOP mode In STOP mode the selected oscillator system clock and peripheral clock is stopped but watch timer can be continued to operate with sub clock With the clock frozen all fu...

Page 219: ...se Timing by External Interrupt 17 4 Released operation of STOP mode After STOP mode is released operation begins according to content of related interrupt register just before STOP mode starts refer to figure 112 If the global interrupt Enable Flag IE EA is set to 1 the STOP mode is released by a certain interrupt of which interrupt enable flag 1 and the CPU jumps to the relevant interrupt servic...

Page 220: ...le 40 Power Down Operation Register Map Name Address Direction Default Description PCON 87H R W 00H Power Control Register 17 6 Register description SET PCON 7 0 SET IEx b STOP Mode IEx b 1 Interrupt Request STOP Mode Release Y Interrupt Service Routine Next Instruction N Corresponding Interrupt Enable Bit IE IE1 IE2 IE3 ...

Page 221: ...Values Normal operation NOTES 1 To enter into IDLE mode PCON must be set to 01H 2 To enter into STOP mode PCON must be set to 03H 3 The PCON register is automatically cleared by a release signal in STOP IDLE mode 4 Three or more NOP instructions must immediately follow the instruction that make the device enter into STOP IDLE mode Refer to the following examples Example 1 Example 2 MOV PCON 01H ID...

Page 222: ...shown in the followings External RESETB Power ON RESET POR WDT Overflow Reset In the case of WDTEN 1 Low Voltage Reset In the case of LVREN 0 OCD Reset 18 1 Reset block diagram In this section reset unit is described in a block diagram Figure 115 Reset Block Diagram 18 2 Power on reset When rising device power POR Power On Reset has a function to reset a device If POR is used it executes the devic...

Page 223: ...ure 117 Internal RESET Release Timing On Power Up VDD nPOR Internal Signal Internal RESETB Oscillation BIT Starts BIT Overflows Slow VDD Rising Time min 0 05V ms VPOR 1 32V Typ VDD nPOR Internal Signal Internal RESETB Oscillation BIT Starts BIT Overflows Fast VDD Rising Time max 50 0V ms ...

Page 224: ...D Internal nPOR PAD RESETB BIT for Configure LVR_RESETB BIT for Reset LSIRC 128kHz 32 LSIRC 128kHz RESET_SYSB Configure Read 250us X 28h 10ms 250us X 40h 16ms F1 Counting for configure option read start after POR is released H LSIRC 128kHz 32 4kHz 250us 00 01 02 03 04 05 00 06 27 28 01 02 00 03 01 02 3F 40 02 03 01 00 External reset have not an effect on counter value for config read ...

Page 225: ...r POR or Ext_reset release Reset Release section BIT overflow I after16ms after External Reset Release External reset II 16ms point after POR POR only BIT is used for Peripheral stability Normal operation 18 3 External resetb input External resetb is input to a Schmitt trigger If the resetb pin is held with low for at least 10us over within the operating voltage range and stable oscillation it is ...

Page 226: ...l during operation by comparing it to a fixed trigger level Trigger level for the BOD can be selected by configuring LVRVS 3 0 bits to be 1 61V 1 68V 1 77V 1 88V 2 00V 2 13V 2 28V 2 46V 2 68V 2 81V 3 06V 3 21V 3 56V 3 73V 3 91V 4 25V In the STOP mode this will contribute significantly to the total current consumption So to minimize the current consumption LVREN bit is set to off by software OSC ST...

Page 227: ...m of LVR Figure 123 Internal Reset at Power Fail Situation LVRVS 3 0 RESET_BODB Brown Out Detector BOD D Q r External VDD LVREN LVRF Low Voltage Reset Flag CPU Write SCLK System CLK nPOR VDD Internal RESETB VDD Internal RESETB VBODMAX VBODMIN 16ms t 16ms 16ms VBODMAX VBODMIN ...

Page 228: ...rator 2 68V 2 81V LVI Circuit LVILS 3 0 3 06V 3 21V 3 56V 3 73V 3 91V 4 25V 2 00V 2 13V 2 28V 1 88V 4 Figure 125 LVI Block Diagram VDD Internal nPOR PAD RESETB BIT for Config LVR_RESETB BIT for Reset LSIRC 128kHz 32 LSIRC 128kHz RESET_SYSB Config Read 250us X 28h 10ms 250us X 40h 16ms F1 F1 H LSIRC 128kHz 32 4kHz 250us H H Main OSC Off 00 01 02 00 3F 40 01 02 01 00 02 03 27 28 ...

Page 229: ...on WDTRF Watch Dog Reset flag bit The bit is reset by writing 0 to this bit or by Power On Reset 0 No detection 1 Detection OCDRF On chip debugger reset flag bit The bit reset by writing 0 to this bit or by Power On Reset 0 No detection 1 Detection LVRF Low Voltage Reset flag bit The bit is reset by writing 0 to this bit or by Power On Reset 0 No detection 1 Detection NOTES 1 When the Power On Res...

Page 230: ...scription 0 0 0 0 1 61V 0 0 0 1 1 68V 0 0 1 0 1 77V 0 0 1 1 1 88V 0 1 0 0 2 00V 0 1 0 1 2 13V 0 1 1 0 2 28V 0 1 1 1 2 46V 1 0 0 0 2 68V 1 0 0 1 2 81V 1 0 1 0 3 06V 1 0 1 1 3 21V 1 1 0 0 3 56V 1 1 0 1 3 73V 1 1 1 0 3 91V 1 1 1 1 4 25V LVREN LVR Operation 0 LVR Enable 1 LVR Disable NOTES 5 The LVRVS 3 0 bits are cleared by a power on reset but are retained by other reset signals 6 The LVRVS 3 0 bits...

Page 231: ...ltage Indicator Flag Bit 0 No detection 1 Detection LVIEN LVI Enable Disable 0 Disable 1 Enable LVIVS 3 0 LVI Level Select LVIVS3 LVIVS2 LVIVS1 LVIVS0 Description 0 0 0 0 Not available 0 0 0 1 Not available 0 0 1 0 Not available 0 0 1 1 1 88V 0 1 0 0 2 00V 0 1 0 1 2 13V 0 1 1 0 2 28V 0 1 1 1 2 46V 1 0 0 0 2 68V 1 0 0 1 2 81V 1 0 1 0 3 06V 1 0 1 1 3 21V 1 1 0 0 3 56V 1 1 0 1 3 73V 1 1 1 0 3 91V 1 1...

Page 232: ...ta EEPROM are Mode Register FEMR Control Register FECR Status Register FESR Time Control Register FETCR Address Low Register x FEARLx Address Middle Register x FEARMx address High Register FEARH They are mapped to SFR area and can be accessed only in programming mode 19 1 1 Register map Table 44 Flash Control and Status Register Map Name Address Dir Default Description FEMR 1020H R W 00H Flash Mod...

Page 233: ...y mode 1 Enable program or program verify mode ERASE Enable erase or erase verify mode with VFY 0 Disable erase or erase verify mode 1 Enable erase or erase verify mode PBUFF Select page buffer 0 Deselect page buffer 1 Select page buffer OTPE Select OTP area instead of program memory 0 Deselect OTP area 1 Select OTP area VFY Set program or erase verify mode with PGM or ERASE Program Verify PGM 1 V...

Page 234: ...ed automatically after 1 clock 0 No operation 1 Start to program or erase of Flash READ Start auto verify of Flash It is cleared automatically after 1 clock 0 No operation 1 Start auto verify of Flash Checksum or CRC16 nFERST Reset Flash control logic It is set automatically after 1 clock 0 Reset Flash control logic 1 No operation default nPBRST Reset page buffer with PBUFF It is set automatically...

Page 235: ...est flag Auto cleared when program erase verify starts Active in program erase verify completion 0 No interrupt request 1 Interrupt request WMODE Write mode flag EMODE Erase mode flag VMODE Verify mode flag FEARL1 Flash address low Register 1 1025H 7 6 5 4 3 2 1 0 ARL17 ARL16 ARL15 ARL14 ARL13 ARL12 ARL11 ARL10 W W W W W W W W Initial value 00H ARL1 7 0 Flash address low 1 FEARM1 Flash address mid...

Page 236: ...d ignored the same least significant bits as the number of bits of page address In auto verify mode address increases automatically by one 2 EARs are write only register Reading these registers returns 24 bit checksum result 3 When calculating flash checksum the lower 4 bits of start address are calculated as 0x0000 and the lower 4 bits of end address as 0x1111 for protection 4 This device can sup...

Page 237: ...ESR 7 L Read 24 bit Checksum H M L Read OCD_XDATA FEARH Read OCD_XDATA FEARM Read OCD_XDATA FEARL Set checksum read mode Write OCD_CODE 0xFAAA 0x55 Write OCD_CODE 0xF555 0xA5 Write OCD_XDATA FEMR 0x81 Write OCD_CODE FETR 0x08 Write OCD_CODE FECR 0x07 Exit checksum read mode Write OCD_XDATA FECR 0x30 Figure 126 Read Device Internal Checksum Full Size ...

Page 238: ...DATA FEARL Set checksum read mode Write OCD_CODE 0xFAAA 0x55 Write OCD_CODE 0xF555 0xA5 Write OCD_XDATA FEMR 0x81 Write OCD_CODE FETR 0x00 Write OCD_CODE FECR 0x07 Exit checksum read mode Write OCD_XDATA FECR 0x30 Write OCD_XDATA FEARM Start Address Upper Write OCD_XDATA FEARL Start Address Lower Write OCD_XDATA FEARM1 End Address Upper Write OCD_XDATA FEARL1 End Address Lower Figure 127 Read Devi...

Page 239: ...to FETCR PEVBSY is cleared when program erase or verify starts and set when program erase or verify stops Max program erase time at INTRC 256 clock 255 1 2 7 8125us 4 0ms In the case of 10 of error rate of counter source clock program or erase time is 3 6 4 4ms Program erase time calculation For page write or erase Tpe TCON 1 2 fLSIRC For bulk erase Tbe TCON 1 4 fLSIRC Recommended bulk erase time ...

Page 240: ...tem program uses the interface of debugger which uses two wires Refer to chapter 20 Development tools in details about debugger 19 3 1 Flash operation F E A R Code Memory PROGRAM 0000h FFFFh P R O G R A M C O U N T E R MUX pgm ers vfy PAGE ADDRESS WORD ADDRESS Program Memory 0x3F 0x00 0x000 0x3FF Page buffer size 64Bytes Page 1023 Page 1022 Page 0 Page 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ...

Page 241: ...re 130 The Sequence of Page Program and Erase of Flash Memory Page Buffer Reset Page Buffer Load 0X00H Erase Erase Latency 500us Page Buffer Reset Configuration Reg setting Cell Read Pass Fail No Page Buffer Reset Page Buffer Load Program PgmLatency 500us Page Buffer Reset ConfigurationReg setting Cell Read Yes Pass Fail Configuration Reg Clear Master Reset In the case of OTP OTPE flag Set In the ...

Page 242: ...ENBDM bit of BCR Enable debug and Request debug mode Read data from Flash Enable program mode Enter OCD ISP mode NOTE1 Set ENBDM bit of BCR Enable debug and Request debug mode Page Buffer Reset Page Buffer Load Configuration Reg 0 Set Erase Latency 500us Page Buffer Reset Configuration Reg 0 clear Reg 6 5 setting Master Reset Erase Cell Read Pass Fail ...

Page 243: ...000_0010 Select page buffer FEMR 1000_1001 Write data to page buffer Address automatically increases by twin Set write mode FEMR 1010_0001 Set page address FEARH FEARM FEARL 20 hx_xxxx Set FETCR Start program FECR 0000_1011 Insert one NOP operation Read FESR until PEVBSY is 1 Repeat to until all pages are written Flash page erase mode Enable program mode Reset page buffer FEMR 1000_0001 FECR 0000_...

Page 244: ...area is erased For bulk erase including OTP area select OTP area set FEMR to 1000_1101 Set FETCR Start bulk erase FECR 1000_1011 Insert one NOP operation Read FESR until PEVBSY is 1 Flash OTP area read mode Enter OCD ISP mode Set ENBDM bit of BCR Enable debug and Request debug mode Select OTP area FEMR 1000_0101 Read data from Flash Flash OTP area write mode Enable program mode Reset page buffer F...

Page 245: ... Write h00 to page buffer Data value is not important Set erase mode and select OTP area FEMR 1001_0101 Set page address FEARH FEARM FEARL 20 hx_xxxx Set FETCR Start erase FECR 0000_1011 Insert one NOP operation Read FESR until PEVBSY is 1 Flash program verify mode Enable program mode Set program verify mode FEMR 1010_0011 Read data from Flash OTP program verify mode Enable program mode Set progra...

Page 246: ...page Flash page erase Erase cell by page Flash bulk erase Erase the whole cells Flash program verify Read cell in verify mode after programming Flash erase verify Read cell in verify mode after erase Flash page buffer load Load data to page buffer 19 4 Mode entrance method of ISP mode 19 4 1 Mode entrance method for ISP Table 47 Mode entrance method for ISP TARGET MODE DSDA DSCL DSDA OCD ISP hC hC...

Page 247: ...x40 at FETCR Table 48 Security Policy using Lock Bits LOCK MODE USER MODE ISP MODE FLASH OTP FLASH OTP LOCKF R W PE BE R W PE BE R W PE BE R W PE BE 0 O O O X X X X X O O O O O O O O 1 O O O X X X X X X X X O O X X O NOTES 1 LOCKF Lock bit of Flash memory 2 R Read 3 W Write 4 PE Page erase 5 BE Bulk Erase 6 O Operation is possible 7 X Operation is impossible 19 6 Configure option For the configure...

Page 248: ...TS Initial value 00H R_P Code Read Protection 0 Disable 1 Enable HL Code Write Protection 0 Disable 1 Enable VAPEN Vector area 00H FFH Protection 0 Disable Protection 1 Enable Protection RSTS Select RESETB pin 0 Disable RESETB pin P55 1 Enable RESETB pin Note Code write protection and Vector area protection are disabled at OCD Mode ...

Page 249: ...63 2Kbytes Address 0100H FDFFH 1 1 1 63 5Kbytes Address 0100H FEFFH Note Specific area write protection are disabled at OCD Mode CONFIGURE OPTION 1 ROM Address 0000H A96G148 A96A148 32K Series 7 6 5 4 3 2 1 0 PAEN PASS2 PASS1 PASS0 Initial value 00H PAEN Enable Specific Area Write Protection 0 Disable Protection 1 Enable Protection PASS 2 0 Select Specific Area for Write Protection NOTE When PAEN ...

Page 250: ...esults to match target applications ABOV supports entire developer ecosystem of the customers 20 1 Compiler ABOV semiconductor does not provide any compiler for the A96G140 A96G148 A96A148 Regarding the compilers it is recommended to consult with your compiler provider Since the A96G140 A96G148 A96A148 has the Mentor 8051 as a core and ROM is smaller than 64Kbytes in size a developer can use any s...

Page 251: ... 94 97 series only Debug Interface OCD 1 OCD 2 Number of Break Point 4 8 Real time Monitoring Yes no OCD 2 only Run Flag Port Yes no OCD 2 option NOTES 1 The A96G140 A96G148 A96A148 has the 96 series core and OCD 1 interface 2 The A96G140 A96G148 A96A148 can be operated with OCD II dongle too because the OCD II dongle includes all of OCD1 functions 3 The 95 series core is the old version of the 96...

Page 252: ...ash Clock Ratio x 1 Pipeline No No 2 stage IF ID EX DHRY Stone Score I8051 1 00 6 0 6 0 8 4 Average Instruction Set Exe Cycle Compare with i8051 x 6 0 x 6 0 x 6 4 Power Consumption DHRY synthesis 52 27uA MHz 52 27uA MHz 30 19 uA MHz NOTES 1 EA means that All Interrupt Enable bit or Disable bit Standard 8051 2 Group When a programmer selects a specific interrupt e g Interrupt1 Whole interrupts 0 6 ...

Page 253: ...cription OCD 1 Break point MAX 8 PC break only OCD 2 Break point MAX 12 With RAM break Code XDATA IDATA 1 8 16 32bit compare Real time monitoring Code XDATA IDATA Frequency output Examine CPU frequency Run Flag port Option for run time measurement 96 Series OCD 1 The 96 series supports basic operation of debug interfaces such as Run Stop Step Break point register reading writing Memory reading wri...

Page 254: ...es 96 Series 97 Series 94 Series Remark Interrupt Priority 6 Grouped 4 Level Fully 4 Level Fully 4 Level 96 Series IP IP Interrupt Priority Register 94 97 Series IPxL IPxH Interrupt Priority Register 96 Series The priority by group is available only with IP IP1 settings With the IP IP1 settings users can set the interrupt priorities in group units The interrupt priority in group units 4 interrupts...

Page 255: ...RAM area for the Stack Pointer The XSPCR decides whether to use XRAM for the Stack Pointer If XSPCR 0 the IRAM is available for the Stack Pointer If XSPCR 1 the XRAM is available for the Stack Pointer The XSP decides a position of XRAM Stack Pointer This is valid only if XSPCR 1 Figure 133 Configuration of Extended Stack Pointer STACK_POINTER XSP 7 0 SP 7 0 XRAM_TOP STACK_SIZE Ex If only 256bytes ...

Page 256: ... and writing Table 55 Debug Feature by Series Series name 96 series 97 series 94 series OCD function OCD 1 OCD 2 OCD 2 Max number of breakpoints 8 8 4 Saving stack in XRAM No Yes Yes Real time monitoring No Yes Yes Run flag support No Yes Yes The OCD 2 applied to the 94 series and 97 series provides the RTM Real Time Monitoring function that monitors internal memory and I O status without stopping...

Page 257: ...ic power supply pin The OCD emulator supports ABOV s 8051 series MCU emulation The OCD uses two wires that are interfaces between PC and MCU which is attached to user s system The OCD can read or change the value of MCU s internal memory and I O peripherals In addition the OCD controls MCU s internal debugging logic This means that the OCD controls emulation step run monitoring and many more funct...

Page 258: ...r programming via the OCD interface Table 57 introduces features of the OCD Table 57 OCD Features Two wire external interface 1 for serial clock input 1 for bi directional serial data bus Debugger accesses All internal peripherals Internal data RAM Program Counter Flash memory and data EEPROM memory Extensive On Chip Debugging supports for Break Conditions Break instruction Single step break Progr...

Page 259: ...t the moment of initialization when the microcontroller is powered on This requires that you can control power of the microcontroller VCC or VDD and need to be careful to place capacitive loads such as large capacity condensers on a power pin Please remember that the microcontroller can enter DEBUG mode only when power is applied and it cannot enter DEBUG mode once the OCD is run Figure 137 Timing...

Page 260: ...tart and end of the communication More detailed information of this communication protocol is listed below Basic transmission packet A 10 bit packet transmission using two pin interface A packet consists of 8 bit data 1 bit parity and 1 bit acknowledge Parity is even of 1 for 8 bit data in transmitter Receiver generates acknowledge bit as 0 when transmission for 8 bit data and its parity has no er...

Page 261: ...valid when the DSDA falls from H to L while External Host maintains the DSCL to H After the valid start bit communication data is transferred and received between a Host and a microcontroller An end bit means end of the data transmission and is valid when the DSDA changes from L to H while a Debugger maintains the DSCL to H Next the microcontroller places the bus in a wait state and processes the ...

Page 262: ...ta is allowed to change when the DSCL is L If the data changes when the DSCL is H the change means START or STOP Figure 140 Bit Transfer on Serial Bus Figure 141 Start and Stop Conditions During the OCD communication each data byte is transferred in accompany with a parity bit When data is transferred in succession a receiver returns the acknowledge bit to inform that it received ...

Page 263: ...ta communications if a microcontroller needs communication delay or process delay it can request communication delay to the Host Debugger Figure 143 shows timing diagrams where a microcontroller requests communication delay to the Host Debugger If the microcontroller requests timing delay of the DSCL signal that the Host Debugger outputs the microcontroller maintains the DSCL signal to L to delay ...

Page 264: ... A96G140 A96G148 A96A148 directly using the E PGM Figure 144 E PGM Single Writer and Pinouts 20 4 2 OCD emulator OCD emulator allows users to write code on the device too since OCD debugger supports In System Programming ISP It doesn t require additional H W except developer s target system 2 VDD 1 3 4 5 6 7 8 10 9 VSS DSCL DSDA ...

Page 265: ...Gang4 and E Gang6 allow users to program multiple devices simultaneously They can be run not only in PC controlled mode but also in standalone mode without the PC control USB interface is available and it is easy to connect to the handler Figure 145 E Gang4 and E Gang6 for Mass Production ...

Page 266: ...able 58 Pins for Flash Programming Pin name Main chip pin name During programming I O Description DSCL P01 I Serial clock pin Input only pin DSDA P00 I O Serial data pin Output port when reading and input port when programming Can be assigned as input push pull output port VDD VSS VDD VSS Logic power supply pin 20 5 1 On board programming Microcontrollers need only four signal lines including VDD ...

Page 267: ...ain Method Wire AND Bi Directional I O Normally it is recommended to place a resister greater than 4 7kΩ for the DSCL and DSDA respectively The capacitive load is recommended to be less than 100pF Outside these ranges because the communication may not be accomplished the connection to Debug mode is not guaranteed Figure 146 Connection of Transmission ...

Page 268: ...mming When you use the OCD pins exclusively or share them with other functions it needs to be careful too Figure 147 shows an example circuit where the OCD pins DSCL and DSDA are shared with other functions They must be connected when debugging or executing In System Program ISP Normally the OCD pins are connected to outside to execute the predefined functions Even when they are connected for debu...

Page 269: ...gnal will be provided to pin DSCL and DSDA And it will cause some damages to the application circuits connected to DSCL or DSDA port if the application circuit is designed as high speed response such as relay control circuit If possible the I O configuration of DSDA DSCL pins had better be set to input mode 2 The value of R1 and R2 is recommended value It varies with circuit of system Figure 147 P...

Page 270: ... A dir Add direct byte to A with carry 2 1 35 ADDC A Ri Add indirect memory to A with carry 1 1 36 37 ADDC A data Add immediate to A with carry 2 1 34 SUBB A Rn Subtract register from A with borrow 1 1 98 9F SUBB A dir Subtract direct byte from A with borrow 2 1 95 SUBB A Ri Subtract indirect memory from A with borrow 1 1 96 97 SUBB A data Subtract immediate from A with borrow 2 1 94 INC A Increme...

Page 271: ...OR indirect memory to A 1 1 46 47 ORL A data OR immediate to A 2 1 44 ORL dir A OR A to direct byte 2 1 42 ORL dir data OR immediate to direct byte 3 2 43 XRL A Rn Exclusive OR register to A 1 1 68 6F XRL A dir Exclusive OR direct byte to A 2 1 65 XRL A Ri Exclusive OR indirect memory to A 1 1 66 67 XRL A data Exclusive OR immediate to A 2 1 64 XRL dir A Exclusive OR A to direct byte 2 1 62 XRL di...

Page 272: ...87 MOV dir data Move immediate to direct byte 3 2 75 MOV Ri A Move A to indirect memory 1 1 F6 F7 MOV Ri dir Move direct byte to indirect memory 2 2 A6 A7 MOV Ri data Move immediate to indirect memory 2 1 76 77 MOV DPTR data Move immediate to data pointer 3 2 90 MOVC A A DPTR Move code byte relative DPTR to A 1 2 93 MOVC A A PC Move code byte relative PC to A 1 2 83 MOVX A Ri Move external data A8...

Page 273: ...2 1 C2 SETB C Set carry 1 1 D3 SETB bit Set direct bit 2 1 D2 CPL C Complement carry 1 1 B3 CPL bit Complement direct bit 2 1 B2 ANL C bit AND direct bit to carry 2 2 82 ANL C bit AND direct bit inverse to carry 2 2 B0 ORL C bit OR direct bit to carry 2 2 72 ORL C bit OR direct bit inverse to carry 2 2 A0 MOV C bit Move direct bit to carry 2 1 A2 MOV bit C Move carry to direct bit 2 2 92 ...

Page 274: ... rel Jump on carry 1 2 2 40 JNC rel Jump on carry 0 2 2 50 JB bit rel Jump on direct bit 1 3 2 20 JNB bit rel Jump on direct bit 0 3 2 30 JBC bit rel Jump on direct bit 1 and clear 3 2 10 JMP A DPTR Jump indirect relative DPTR 1 2 73 JZ rel Jump on accumulator 0 2 2 60 JNZ rel Jump on accumulator 0 2 2 70 CJNE A dir rel Compare A direct jne relative 3 2 B5 CJNE A d rel Compare A immediate jne rela...

Page 275: ...memory 1 2 A5 TRAP Software break command 1 1 A5 In the above table entries such as E8 EF indicate continuous blocks of hex opcodes used for 8 different registers Register numbers of which are defined by the lowest three bits of the corresponding code Non continuous blocks of codes shown as 11 F1 for example are used for absolute jumps and calls with the top 3 bits of the code being used to store ...

Page 276: ...gh Internal RC Oscillator Characteristics on page 246 Updated 19 4 Power on Reset Characteristics on page 245 Updated 19 5 Low Voltage Reset and Low Voltage Indicator Characteristics on page 245 2020 02 04 1 14 Added the disclaimer and modified the distributor 2020 02 06 1 15 Revised A96G14x to A96G140 A96G148 2020 02 18 1 16 Added to A96A148 device 2020 02 21 1 17 Corrected typographical errors 2...

Page 277: ...nfiguration Timing when Power on and Figure 124 Configuration Timing When LVR RESET 2021 03 05 1 27 Added 48 QFN package at 22 Package information and 23 Ordering information 2021 03 11 1 28 Changed the value of total power dissipation PT from 600 mW to 800 mW in Absolute Maximum Ratings Deleted the table of Input Output Capacitance in Electrical Characteristics 2021 04 23 1 29 Changed the figures...

Page 278: ... and shall not be responsible or liable for any injuries or damages related to use of ABOV products in such unauthorized applications ABOV and the ABOV logo are trademarks of ABOV All other product or service names are the property of their respective owners Information in this document supersedes and replaces the information previously supplied in any former versions of this document 2020 ABOV Se...

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