manualshive.com logo in svg

Abov A31G22x, Manual, Page: 23 / 29

Share
Download
Abov A31G22x Manual Download Page 23

A31G22x Clock Setting Guide

 

 

5. Flash Access Timing

 

 

23 

5.

 

Flash Access Timing 

5.1.

 

Wait Time Configuration 

Users of A31G22x can set the Wait-time in WAIT field (CFMC_CFG[10:8]) of the CFMC_CFG register 
after setting the system main clock. The Wait-time settings implies the Flash access speed and affects 
system performance. 

Users can set the Access Timing of Code Flash Memory and Data Flash Memory to the value between 
0-wait and 5-wait. In addition, the Access Timing can be calculated by the following formula depending 
on the system main clock (MCLK = HCLK) and the Wait time. 

𝐹𝑙𝑎𝑠ℎ 𝐴𝑐𝑐𝑒𝑠𝑠 𝑇𝑖𝑚𝑖𝑛𝑔 =

𝐻𝐶𝐿𝐾

1 + 𝑊𝐴𝐼𝑇

≤ 20𝑀𝐻𝑧

 

 

Table 7. Flash Wait Time Values 

Register Field 

WAIT Value  Description 

Max.  Flash  Access 
Speed 

CFMC_CFG<WAIT> 
or   
DFMC_CFG<WAIT> 

0 

Flash access in 1 cycle (0-wait) 

Up to 20MHz 

1 

Flash access in 2 cycles (1-wait) 

Up to 40MHz 

2 

Flash access in 3 cycles (2-wait) 

Up to 48MHz 

3 

Flash access in 4 cycles (3-wait) 

Up to 48MHz 

4 

Flash access in 5 cycles (4-wait) 

Up to 48MHz 

5, Others 

Flash access in 6 cycles (5-wait) 

Up to 48MHz 

 

5.2.

 

F/W Configuration 

Figure 12 shows an example code that sets Flash Access Timing. Set the Flash Wait Delay to 2 for the 
system having 48MHz of MCLK. For this case, the Flash Access Speed is 16MHz as calculated below: 

48MHz / (1 + 2) = 16MHz (62.5ns) 

 

Figure 12. Flash Access Timing F/W Configuration 

 

Summary of Contents for A31G22x

Page 1: ...Global Top Smart MCU Innovator ABOV Semiconductor www abovsemi com A31G22x Clock Setting Guide Application Note Version 1 01...

Page 2: ...F W Configuration 12 4 3 LSE Clock 13 4 3 1 H W Configuration 13 4 3 2 F W Configuration 14 4 4 HSE Clock 15 4 4 1 H W Configuration 15 4 4 2 F W Configuration 16 4 5 PLL Clock 17 4 5 1 PLL Block Dia...

Page 3: ...17 Figure 10 PLL Clock F W Configuration Example 1 19 Figure 11 PLL Clock F W Configuration Example 2 21 Figure 12 Flash Access Timing F W Configuration 23 Figure 13 System Main Clock Output 24 Figure...

Page 4: ...PCLK APB Clock MCLK Main Clock LSI Low Speed Internal Clock HSI High Speed Internal Clock LSE Low Speed External Clock HSE High Speed External Clock PLL Phase Locked Loop Clock XTAL External Crystal S...

Page 5: ...ication Specifically the SCU allows users to configure a main system clock by selecting and setting a clock source for the user system In this application note users can learn a method to select a cor...

Page 6: ...other is PCLK using APB bus which produces a clock signal for peripheral systems Table 2 Main Clock Branches Clock Source Clock Bus Description Modules MCLK HCLK High Speed Clock Bus Core Flash Memor...

Page 7: ...TSSENSECLK TSREFCLK M U X MCLK M U X PCLK PLLBYPASS PLLOUTPUT NOTES 1 In the block diagram above peripheral blocks not specified in the SCU_MCCRx register use PCLK as a reference clock by default 2 I...

Page 8: ...PCLK END Peripheral clock MCCRn Select clock for Peripheral In SCU_PPCLKSR Select MCCRn for the Peripheral to use Y Peripheral clock PCLK Exception WT WDT LCD N WT LSE WDTRC WDT WDTRC LCD LSE WDTRC S...

Page 9: ...ls Peripheral Clock Clock Bus Clock Source Core HCLK CFMC HCLK PCLK DFMC HCLK PCLK DMAC HCLK PCLK CRC PCLK SysTick HCLK SCU_MCCR1 LSI HSI LSE HSE MCLK PLL TIMER1n PCLK SCU_MCCR1 LSI HSI LSE HSE MCLK P...

Page 10: ...DTRC LSI 16 SCU_MCCR3 LSI HSI LSE HSE MCLK PLL PCU PCLK PCU Debounce Clock SCU_MCCR4 LSI HSI LSE HSE MCLK PLL USART PCLK UART PCLK SPI PCLK I2C PCLK LCD PCLK WDTRC LSI 16 SCU_MCCR5 LSI HSI LSE HSE MCL...

Page 11: ...ng these clock sources Table 4 Definition of Clock Sources Clock source Frequency Range Clock Bus Supply Voltage V LSI 500kHz 20 Main clock Peripheral clock WDTRC Divided by 16 1 8 to 5 5 HSI 32MHz 1...

Page 12: ...users can implement user application system with a low cost and effective solution 4 1 1 F W Configuration Right after applying power although the LSI clock is in Always On but explicitly the LSI cloc...

Page 13: ...erations that makes accurate time measurement The RTC is realized by dividing the clock using the pre scaler and usually required for Time Critical System Tolerance of the LSE clock reflects the chara...

Page 14: ...be set before enabling the LSE clock After enabling the LSE clock stabilization time for the SXTAL is required Next users must set the LSE clock source as the system clock and update the global variab...

Page 15: ...the main external crystal XTAL as shown in Figure 7 Please remember that the External Load Caps C1 and C2 in the figure are varied by the value of minimum operation voltage and XTAL frequency of the a...

Page 16: ...be set before enabling the HSE clock After enabling the HSE clock stabilization time for the XTAL is required Next users must set the HSE clock source as the system clock and update the global variabl...

Page 17: ...cy 4 5 1 PLL Block Diagram R PFD CP VCO LPF N1 D N2 P POR LOCK DETECT PLLEN PLLRSTB fPLLINCLK PLLLOCK RST_I fDOUBLE fVCO x 2 fVCO EN PORST VCTRL PLLRSTB BYPASSB PLLINCLK fPLLOUT 0 1 fIN NOTES 1 Set PL...

Page 18: ...2MHz At this time the range of fVCO output frequency should be set to 200MHz or less and the calculation formula is shown below VCO IN N1 1 VCO 200MHz The SCU_PLLCON register also supports the Doubler...

Page 19: ...LINCLK 32MHz is used without change since the fIN ranges from 1MHz to 3MHz and the value of PREDIV R can be between 0 and 7 at this time the fPLLINCLK clock that is HSI clock is divided by 2 in the SC...

Page 20: ...et BYPASSB bit to enable PLL Output Bypass mode Set PLLEN and PLLRSTB bits to enable PLL and PLL Reset Set PREDIV to the value that you defined for the PLL Divider in the step3 Option Update the SCU_P...

Page 21: ...at operates with 8MHz XTAL Figure 11 PLL Clock F W Configuration Example 2 1 Set XIN and XOUT pins and enable HSE clock source At this time fPLLINCLK is 8MH fPLLINCLK 8MHz 1 8MHz SCU_CSCR HSECON 3 0 0...

Page 22: ...r Set BYPASSB bit to enable PLL Output Bypass mode Set PLLEN and PLLRSTB bits to enable PLL and PLL Reset Set PREDIV to the value that you defined for the PLL Divider in the step3 Update the SCU_PLLCO...

Page 23: ...clock MCLK HCLK and the Wait time 1 20 Table 7 Flash Wait Time Values Register Field WAIT Value Description Max Flash Access Speed CFMC_CFG WAIT or DFMC_CFG WAIT 0 Flash access in 1 cycle 0 wait Up t...

Page 24: ...s an Alternative Function and select a CLKO function 2 Configure the SCU_COR register to enable the CLKO Divider and set its value Set CLKOEN bit to 1 This means CLKO is enabled Set CLKODIV bits to th...

Page 25: ...System Main Clock 25 Users can measure the signal at the CLKO pin PF4 by connecting an oscilloscope probe The signal is about 50kHz Pulse Wave resulted from the LSI clock divided by 10 Figure 14 Osci...

Page 26: ...initialization Figure 15 Example Project Changing System Clock When the power is applied to the system 500kHz of LSI operates In operation of the main the main clock is initialized by the function Sys...

Page 27: ...A31G22x Clock Setting Guide 8 References 27 8 References A31G22x User s Manual A31G22x Datasheet...

Page 28: ...1G22x Clock Setting Guide 28 Revision History Version Date Description 1 00 20 12 10 Initial preliminary version created 1 01 21 01 18 Revised description in 3 1 Figure 2 4 3 4 4 and 4 5 Added CLKO fo...

Page 29: ...nd shall not be responsible or liable for any injuries or damages related to use of ABOV products in such unauthorized applications ABOV and the ABOV logo are trademarks of ABOV All other product or s...

Reviews:

No comments