A31G22x Clock Setting Guide
4. Clock Sources
17
4.5.
PLL Clock
PLL clock is used to set the high speed clock frequency as a main clock of the system. The two clock
sources HSI and HSE are used as Input clocks of the PLL.
Tolerance of PLL reflects the characteristics of the input clock sources. Based on the PLL input clocks,
PLL Frequency Divider can be used to output more accurate frequency, and the main clock of the
system can be set up to 48MHz using PLL Output Frequency.
4.5.1.
PLL Block Diagram
R
PFD
CP
VCO
LPF
N1
D
N2
P
POR
LOCK
DETECT
PLLEN
PLLRSTB
f
PLLINCLK
PLLLOCK
RST_I
f
DOUBLE
(f
VCO
x 2)
f
VCO
EN
PORST
V
CTRL
PLLRSTB
BYPASSB
PLLINCLK
f
PLLOUT
0
1
f
IN
NOTES:
1.
Set PLLRSTB to ‘1’ after at least 1us when PLLEN is set to ‘1’.
2.
(Option) Wait at least 100 us after PLLLOCK is occurred.
3.
Output calculation formula is as followings:
𝑓
OUT
=
𝑓
𝑃𝐿𝐿𝐼𝑁𝐶𝐿𝐾
× (N
1
+ 1)
(R + 1) × (N
2
+ 1) × (P + 1)
∗ (D + 1)
Name
Symbol
Description
Setting Range
PREDIV
R
PLLINCLK Pre-Divider Value
0 to 7
POSTDIV1
N
1
Post Multiplier Value
0 to 255
POSTDIV2
N
2
Post Divider Value
0 to 15
OUTDIV
P
Output Divider Value
0 to 15
PLLMODE
D
Frequency Doubler Value
0 to 11
Figure 9. PLL Block Diagram of A31G22x Series