BIOS Setup
3-9
3-4. Advanced Chipset Features
DRAM Timing Selectable:
This item sets the optimal timings for the following four items, depending on the memory module you are
using. The default setting “By SPD” configures these four items by reading the contents in the SPD
(Serial Presence Detect) device. The EEPROM on the memory module stores critical parameter
information about the module, such as memory type, size, speed, voltage interface, and module banks.
CAS Latency Time (tCL):
This item controls the latency between the DRAM read command and the time that the data becomes
actually available.
RAS# to CAS# Delay (tRCD)
This item controls the latency between the DRAM active command and the read/write command.
RAS# Precharge (tRP):
This item controls the idle clocks after issuing a precharge command to the DRAM.
Precharge Delay (tRAS)
This item controls the number of DRAM clocks used for the DRAM parameters.
Memory Hole At 15M-16M:
When set to [Enabled], the memory address space at 15M-16M will be reserved for ISA expansion cards
that specifically requires this setting. This makes the memory from 15MB and up unavailable to the
system. Leave this item to its default setting.
User’s Manual
Summary of Contents for IL8
Page 1: ...IL8 Intel Pentium 4 System Board Socket 775 User s Manual 4310 0000 40 Rev 2 00 ...
Page 7: ...Introduction 1 3 1 2 Layout Diagram User s Manual ...
Page 8: ...1 4 Chapter 1 1 4 Chapter 1 IL8 IL8 ...
Page 46: ...A 2 Appendix A A 2 Appendix A IL8 IL8 ...
Page 48: ...B 2 Appendix B B 2 Appendix B IL8 IL8 ...
Page 50: ...C 2 Appendix C IL8 ...
Page 52: ...D 2 Appendix D D 2 Appendix D IL8 IL8 ...
Page 54: ...E 2 Appendix E IL8 ...
Page 56: ...F 2 Appendix F IL8 ...
