ABELL A-82 UHF Service Manual
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SP
IF AMP
DET
DET
IC301
LPF
FM IF IC IC300
AF AMP
IC401
LPF
HPF
Q404
SW
AF PA AMP
IC2
Q4,Q5
SW
Q303
W/N SW
IC301
LPF
QT/DQT
IC1
CPU
B
U
S
Y
M
U
T
E
A
F
C
C
T
I
图
3
音音音音音音音音音音音音
W/N
6
）
Receive signaling
QT/DQT
300Hz and higher audio frequencies of the output signal from IF IC are cut by IC301. Then, the
signal is input into IC1. IC1 determines whether the QT or DQT matches the preset value, and controls
the MUTE, AFCC and the speaker output sounds according to the squelch results.
3
．
PLL frequency synthesizer
The PLL circuit generates the first local oscillator signal for reception and the RF signal for
transmission.
1
）
PLL
The frequency step of the PLL circuit is 5 or 6.25 kHz. A 12.8 MHz reference oscillator signal is divided
at IC100 by a fixed counter to produce the 5 or 6.25 kHz reference frequency. The voltage controlled
oscillator (VCO) output signal is buffer amplified by Q105, then divided in IC100 by a dual-module
programmable counter. The divided signal is compared in phase with the 5 or 6.25 kHz reference
signal in the phase comparator in IC100. The output signal from the phase comparator is filtered
through a low-pass filter and though the VCO to control the oscillator frequency.
（
See the chart 7
）
2
）
VCO
The operating frequency is generated by Q101 in transmit mode and Q104 in receive mode. The
oscillator frequency is controlled by applying the VCO control voltage, to the varactor diodes (D102
and D103 in receive mode and D100 and D101 in transmit mode). In receive mode, the voltage of
Q104 is provided by closing the Q14. In transmit mode, the voltage of Q101 is provided by opening
Q14 and closing Q13.
【
Closing or opening of Q14 is controlled by the high or low level output of
CPU(IC2 Pin 32), in receive mode, CPU(IC2 Pin 32) output high level, in transmit mode, CPU(IC2 Pin
32) output low level
】
,The outputs from Q104 and Q101 are amplified by Q102 and sent to the buffer
amplifiers.
Chart 6. Audio AMP and noise reducing circuit
