be on the bus side, so that series capacitor appears between the IED point and fault on the
presents the corresponding phasor diagrams for the cases with
bypassed and fully inserted series capacitor.
Voltage distribution on faulty lossless serial compensated line from fault point F to the bus is
linearly dependent on distance from the bus, if there is no capacitor included in scheme (as
shown in figure
). Voltage U
M
measured at the bus is equal to voltage drop
D
U
L
on the faulty
line and lags the current I
F
by 90 electrical degrees.
The situation changes with series capacitor included in circuit between the IED point and the
fault position. The fault current I
F
(see figure
) is increased due to the series capacitor,
generally decreases total impedance between the sources and the fault. The reactive voltage
drop
D
U
L
on X
L1
line impedance leads the current by 90 degrees. Voltage drop
D
U
C
on series
capacitor lags the fault current by 90 degrees. Note that line impedance X
L1
could be divided
into two parts: one between the IED point and the capacitor and one between the capacitor
and the fault position. The resulting voltage U
M
in IED point is this way proportional to sum of
voltage drops on partial impedances between the IED point and the fault position F, as
presented by
(
)
1
=
×
-
M
F
L
C
U
I
j X
X
EQUATION1901 V1 EN-US
(Equation 70)
en06000605.vsd
~
Z<
X
S
X
L1
I
F
U
U
M
Source
Fault voltage
Pre -fault voltage
X
C
Source voltage
U’
M
With bypassed
capacitor
With inserted
capacitor
F
IEC06000605 V1 EN-US
Figure 94: Voltage inversion on series compensated line
en06000606.vsd
I
F
U
S
U
’
M
=
x
U
L
x
U
S
I
F
x
U
L
U
S
x
U
C
U
M
x
U
S
With bypassed
capacitor
With inserted
capacitor
IEC06000606 V1 EN-US
Figure 95: Phasor diagrams of currents and voltages for the bypassed and inserted
series capacitor during voltage inversion
Section 7
1MRK 505 343-UEN B
Impedance protection
164
Application manual
Summary of Contents for Relion 670 series
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