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abaco systems PCI-5565PIORC Hardware Reference Manual Download Page 58

58 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts

Publication No. 500-9367855565-000 Rev. D.0

3.3.13 Interrupt 2 Sender ID FIFO

Interrupt 2 Sender ID FIFO (SID2) BAR2 (Offset $2C): An 8-bit FIFO functioning
just like SID1, except it responds only to type 2 network interrupts.

3.3.14 Interrupt 3 Sender Data FIFO

Interrupt 3 Sender Data FIFO (ISD3) BAR2 (Offset $30): A 32-bit FIFO functioning
just like ISD1, except it responds only to type 3 network interrupts.

3.3.15 Interrupt 3 Sender ID FIFO

Interrupt 3 Sender ID FIFO (SID3) BAR2 (Offset $34): An 8-bit FIFO functioning
just like SID1, except it responds only to type 3 network interrupts.

3.3.16 Interrupt 4 Sender Data FIFO

Interrupt 4 Sender Data FIFO (ISD4) BAR2 (Offset $38): A 32-bit FIFO functioning
just like ISD1, except it responds only to type 4 network interrupts.

3.3.17 Interrupt 4 Sender ID FIFO

Interrupt 4 Sender ID FIFO (SID4) BAR2 (Offset $3C): An 8-bit FIFO functioning
just like SID1, except it responds only to type 4 network interrupts.

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Summary of Contents for PCI-5565PIORC

Page 1: ...Ultrahigh Speed Fiber Optic Reflective Memory with Interrupts THE PCI 5565PIORC IS DESIGNED TO MEET THE EUROPEAN UNION EU RESTRICTIONS OF HAZARDOUS SUBSTANCE RoHS DIRECTIVE 2002 95 EC CURRENT REVISION Publication No 500 9367855565 000 Rev D 0 ...

Page 2: ...re Reference Manual D 0 October 2016 Reformatted Abaco Systems is registered with an approved Producer Compliance Scheme PCS and subject to suitable contractual arrangements being in place will ensure WEEE is processed in accordance with the requirements of the WEEE Directive Abaco Systems will evaluate requests to take back products purchased by our customers before August 13 2005 on a case by ca...

Page 3: ... numbers have a b subscript The prefix 0x shows a hexadecimal number following the C programming language convention Thus One dozen 12D 0x0C 1100b The multipliers k M and G have their conventional scientific and engineering meanings of x103 x106 and x109 respectively The only exception to this is in the description of the size of memory areas when k M and G mean x210 x220 and x230 respectively NOT...

Page 4: ...uments Refer to PCI Local Bus Specification for a detailed explanation of the PCI Local bus from the following source PCI Local Bus Specification Rev 2 2 PCI Special Interest Group P O Box 14070 Portland OR 97214 800 433 5177 U S 503 797 4207 International 503 234 6762 FAX For information on PLD Applications PCI X IP Core contact them at United States PLD Applications Inc 2570 North First St 2nd f...

Page 5: ...ORCs along with other members of this family can be integrated into a network using standard fiber optic cables Each board in the network is referred to as a node Reflective Memory allows computers workstations PLCs and other embedded controllers with different architectures and dissimilar operating systems to share data in real time The 5565 family of Reflective Memory referred to as RFM 5565 in ...

Page 6: ...ue of 5565 which is Abaco s board type Subsystem Vendor ID and Subsystem ID The PCI Configuration register reserved for the subsystem vendor ID has the value of 1556 which designates PLD applications The PCI Configuration register reserved for the subsystem ID has the value of 0080 which is the PLD Applications PCI X core identification number Comparison of the PCI 5565PIORC and the PCI 5565 The c...

Page 7: ...he other hand contains both groups of registers within the same FPGA The two groups could have been combined However to provide software continuity and backward compatibility the two register groups have been maintained separately as in the classic VMIPCI 5565 Further the individual bit functions within the registers where applicable are still compatible The PCI 5565PIORC does not include a second...

Page 8: ...errupts Publication No 500 9367855565 000 Rev D 0 Block Diagram Figure 1 Block Diagram of PCI 5565PIORC 133 MHz Memory 32 bit Data SERDES 106 25 MHz 16 bit 2 125 GHz Optics Fiber Optic Network 4 bit Parity PCI bus Rx Tx FIFO FIFO Main FPGA PCI Core 32 64 bit at 33 66 MHz ...

Page 9: ...ve Memory Network PCI WorkStation with PCI 5565PIORC NODE 1 PCI 5565PIORC VMEbus Chassis with PMC 5565PIORC NODE 255 Up to 300m between nodes for multimode VMEbus Chassis with VMIVME 5565 NODE 0 VM IVME VM IVME 5565 5565 VMIVME 5565 PMC 5565PIORC Up to 10km between nodes for single mode ...

Page 10: ...cal ground safety ground at the power outlet Do Not Operate in an Explosive Atmosphere Do not operate the system in the presence of flammable gases or fumes Operation of any electrical system in such an environment constitutes a definite safety hazard Keep Away from Live Circuits Operating personnel must not remove product covers Component replacement and internal adjustments must be made by quali...

Page 11: ...1000 4 2 IEC61000 4 3 International Compliance It has also met the following international levels European Union BS EN55024 1998 w A1 01 A2 03 CISPR22 EN55022 Class A CISPR11 EN55011 Class A Group 1 United States FCC Part 15 Subpart B Section 109 Class A CISPR 22 1997 Class A ANSI C63 4 2003 method Australia New Zealand AS NZS CISPR 22 2002 Class A using EN55022 1998 Class A Japan VCCI April 2005 ...

Page 12: ...erference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to co...

Page 13: ...iguration Registers 41 3 3 RFM Control and Status Registers 48 3 3 1 Board Revision Register 49 3 3 2 Board ID Register 49 3 3 3 Board Revision Build Register 49 3 3 4 Node ID Register 49 3 3 5 Local Control and Status Register 1 49 3 3 6 Local Interrupt Control Registers 53 3 3 7 Network Target Data Register 56 3 3 8 Network Target Node Register 56 3 3 9 Network Interrupt Command Register 56 3 3 ...

Page 14: ...l Reflective Memory Network 9 Figure 1 1 S1 and S2 Location PCI 5565PIORC 20 Figure 1 2 Installing the PCI 5565PIORC 21 Figure 1 3 Front Panel of PCI 5565PIORC 22 Figure 1 4 LC Type Fiber Optic Cable Connector 24 Figure 1 5 Example Six Node Ring Connectivity PCI 5565PIORC 24 Figure 2 1 Interrupt Circuitry Block Diagram 28 Figure 3 1 Block Diagram of the Network Interrupt Reception Circuitry 59 ...

Page 15: ...Register 3 for Access to Reflective Memory 38 Table 3 15 PCI Base Address Register 4 38 Table 3 16 PCI Base Address Register 5 39 Table 3 17 PCI Cardbus CIS Pointer Register 39 Table 3 18 PCI Subsystem Vendor ID Register 39 Table 3 19 PCI Subsystem ID Register 39 Table 3 20 PCI Expansion ROM Base Register 39 Table 3 21 PCI Capability Pointer Register 40 Table 3 22 PCI Interrupt Line 40 Table 3 23 ...

Page 16: ... the Local Control and Status Registers 48 Table 3 43 Local Control and Status Register 1 49 Table 3 44 PCI PIO Window Sizes 51 Table 3 45 Config 1 and Config 0 Memory Size 51 Table 3 46 Offset 1 and Offset 0 52 Table 3 47 Local Interrupt Status Register 53 Table 3 48 Local Interrupt Enable Register 56 Table 3 49 Network Interrupt Command Register 57 Table 3 50 DMA Registers 60 Table 3 51 DMA Chan...

Page 17: ...r broken components damaged printed circuit board s heat damage and other visible contamination All claims arising from shipping damage should be filed with the carrier and a complete report sent to Abaco Systems Customer Care 1 2 Handling Precaution Some of the components assembled on Abaco s products may be sensitive to electrostatic discharge and damage may occur on boards that are subjected to...

Page 18: ...ed from the ring when two or more nodes are configured with Rogue Master 0 enabled and that data will be lost NOTE No more than one node on the ring should be configured with Rogue Master 1 enabled Certain packets will be removed from the ring when two or more nodes are configured with Rogue Master 1 enabled and that data will be lost Prior to installing the RFM 5565 in the host system switch S1 m...

Page 19: ...FF OFF 10 16 OFF OFF OFF OFF ON OFF OFF OFF 8 8 OFF OFF OFF OFF OFF ON OFF OFF 4 4 OFF OFF OFF OFF OFF OFF ON OFF 2 2 OFF OFF OFF OFF OFF OFF OFF ON 1 1 OFF OFF OFF OFF OFF OFF OFF OFF 0 0 Factory Default S2 positions 1 through 8 OFF Table 1 2 Switch S1 Configuration RFM 5565 Position 1 OFF non redundant mode Position 1 ON redundant mode Position 2 OFF higher performance achievable Position 2 ON l...

Page 20: ...20 PCI 5565PIORC Ultrahigh Speed Fiber Optic Reflective Memory with Interrupts Publication No 500 9367855565 000 Rev D 0 Figure 1 1 S1 and S2 Location PCI 5565PIORC ...

Page 21: ...e ID has been set prior to installation Also setup the board for the desired mode of operation See Section 1 3 ʺSwitch S1 and S2 Configurationʺ 2 Install the PCI 5565PIORC firmly into the PCI connectors refer to Figure 1 2 for installation of the PCI 5565PIORC Install the screw to secure the PCI 5565PIORC to the chassis 3 Close the system chassis apply power Figure 1 2 Installing the PCI 5565PIORC...

Page 22: ...he port labeled TX is the transmitter The PCI 5565PIORC uses LC type fiber optic cables Figure 1 3 Front Panel of PCI 5565PIORC CAUTION When fiber optic cables are not connected the supplied dust caps need to be installed to keep dust and dirt out of the optics Do not power up the PCI 5565PIORC without the fiber optic cables installed This could cause eye injuries TX RX PCI 5565 PIORC STATUS SIG D...

Page 23: ...glemode fiber optic interface Figure 1 4 is an illustration of the LC type multimode or singlemode fiber optic connector 1 6 1 Connector Specification Singlemode and Multimode Compatible with LC standard and JIS C 5973 compliant Ceramic ferrule Temperature range 20 C to 85 C Table 1 4 LED Descriptions LED Color Description Status Red User defined board status indicator Signal Detect Yellow Indicat...

Page 24: ...de Ring Connectivity PCI 5565PIORC 0 84 21 23 0 49 1 25 Dimensions inches mm 4 5mm STATUS SIG DET OWN DATA TX RX PCI 5565 PIORC STATUS SIG DET OWN DATA TX RX PCI 5565 PIORC STATUS SIG DET OWN DATA TX RX PCI 5565 PIORC STATUS SIG DET OWN DATA TX RX PCI 5565 PIORC STATUS SIG DET OWN DATA TX RX PCI 5565 PIORC STATUS SIG DET OWN DATA TX RX PCI 5565 PIORC Node 1 Node 2 Node 6 Node 5 Node 4 Node 3 ...

Page 25: ...e write can be as simple as a PIO target write or it can be due to a DMA cycle by the resident DMA engine While the write to the SDRAM is occurring circuitry on the RFM 5565 automatically writes the data and other pertinent information into the transmit FIFO From the transmit FIFO the transmit circuit retrieves the data and puts it into a variable length packet of 4 to 64 bytes that is transmitted...

Page 26: ...gisters Local Configuration Registers Base Address Register 0 has the starting address for register memory space accesses and Base Address Register 1 has the starting address for register IO space accesses Some Local Configuration Registers pertinent to the RFM 5565 s operation include the Interrupt Control and Status Register INTCSR and the DMA Control Registers RFM Control and Status Registers T...

Page 27: ... 1 DMA Ch 0 Done 2 Local Interrupt Input LINTi The primary tier interrupt source 1 is used during DMA cycles and must be configured in the DMA registers The other primary tier interrupt source 2 is the Local Interrupt Input LINTi All secondary tier interrupts are funneled through the LINTi Second tier interrupts include several operational status bits faults and network interrupts The second tier ...

Page 28: ... s 4 Local Interrupt Status Register LISR Offset 10 Local Interrupt Enable Register LIER Offset 14 RFM Control and Status Registers per Base Address Register 2 RFM Fault Status Events LINT Second Tier Interrupts Interrupt Control and Status Register INTCSR Offset 68 Bits 11 and 15 DMA 0 Done Bits 18 and 21 Host Interrupt INTA RFM Control and Status Registers per Base Address Register 0 or 1 Primar...

Page 29: ...t of the board Instead it sets a bit in the LISR register which will result in a PCI interrupt if enabled The actual board reset should be performed by the host system in an orderly fashion However the user application could use this network interrupt for any purpose 2 7 Redundant Transfer Mode of Operation The RFM 5565 is capable of operating in a redundant transfer mode The board is configured f...

Page 30: ...due to true component failure or due to operation in an overly harsh environment Normally the solution is to isolate and replace the malfunctioning board and or improve the environment However some users prefer to tolerate sporadic rogue packets rather than halt the system for maintenance provided the rogue packets are removed from the network To provide tolerance for rogue packet faults the RFM 5...

Page 31: ... register sets and the Reflective Memory The location of the register sets and the Reflective Memory varies from system to system and can even vary from slot to slot within a system For operations beyond the basic setup such as enabling or disabling interrupts or performing DMA cycles the user must know the specific bit assignments of the registers within the three register sets That information i...

Page 32: ...accessible at all times they are rarely altered by the user NOTE All registers can be accessed as a Byte Word or Double word request Table 3 1 PCI Configuration Registers Address Hex 31 24 23 16 15 8 7 0 00 Device ID Vendor ID 04 Status Register Command Register 08 Class Code Revision ID 0C BIST Header Type Latency Timer Cache Line Size 10 Base Address Register 0 14 Base Address Register 1 18 Base...

Page 33: ...cle Not Supported Yes No 0 4 Reserved N A N A 0 5 VGA Palette Snoop Not Supported Yes No 0 6 Parity Error Response Writing a zero 0 indicates parity error is ignored and the operation continues Writing a one 1 indicates parity checking is enabled Yes Yes 0 7 Wait Cycle Control Controls whether a device does address data stepping A zero 0 indicates the device never does stepping A one 1 indicates t...

Page 34: ... Reflective Memory acting as a master when it detects a data parity error if parity error response bit is set Yes Yes Clr 0 10 9 DEVSEL Timing Hardwired to Binary 10 Devsel timing is slow Yes No 10 11 Target Abort When set to one 1 indicates the Reflective Memory has signaled a Target Abort Writing a one 1 clears this bit to zero 0 Yes Yes Clr 0 12 Received Target Abort When set to one 1 indicates...

Page 35: ...e Size Specified in units of 32 bit words 8 or 16 Dwords Yes Yes 0 NOTE This register can be altered by the system BIOS during the system boot process Table 3 8 PCI Latency Timer Register PCI Latency Timer Offset 0D Bit Description Read Write Value after PCI Reset 7 0 PCI Bus Latency Timer Specified amount of time in units of PCI bus clocks the Reflective Memory as a bus master can burst data on t...

Page 36: ...e The software should fail device if BIST is not complete after two seconds Refer to the Runtime registers for interrupt Control and Status Yes Yes 0 7 BIST Support Returns a one 1 if device supports BIST Returns a zero 0 if device is not BIST compatible Yes No 0 Table 3 11 PCI Base Address Register 0 for Access to Local Configuration Registers PCIBAR0 Offset 10 Bit Description Read Write Value af...

Page 37: ...NOTE This register will be altered by the system BIOS during the system boot process Table 3 13 PCI Base Address Register 2 for Access to RFM Control and Status Registers PCIBAR2 Offset 18 Bit Description Read Write Value after PCI Reset 0 Memory Space Indicator A zero 0 indicates the register maps into Memory Space A one 1 indicates the register maps into I O Space Yes No 0 2 1 Register Location ...

Page 38: ... reserved and remain unaltered by the user Table 3 14 PCI Base Address Register 3 for Access to Reflective Memory PCIBAR3 Offset 1C Bit Description Read Write Value after PCI Reset 0 Memory Space Indicator Writing zero 0 indicates the register maps into Memory Space Writing a one 1 indicates the register maps into I O Space Yes No 0 2 1 Register Location Values 00 Locate anywhere in 32 bit Memory ...

Page 39: ... a PLD Application Table 3 19 PCI Subsystem ID Register PCI Subsystem ID Offset 2E Bit Description Read Write Value after PCI Reset 15 0 Subsystem ID unique add in board device ID Yes No 0080 NOTE The value 0080 denotes a PLD Application PCI X core Table 3 20 PCI Expansion ROM Base Register PCI Expansion ROM Base Offset 30 Bit Description Read Write Value after PCI Reset 0 Address Decode Enable A ...

Page 40: ...oller s is connected to each interrupt line of the device Yes Yes 0 NOTE This register will be altered by the system BIOS during the system boot process Table 3 23 PCI Interrupt Pin PCI Interrupt Pin PCIIPR Offset 3D Bit Description Read Write Value after PCI Reset 7 0 Interrupt Pin Register Indicates which interrupt pin the device uses The following values are decoded the Reflective Memory suppor...

Page 41: ...bility with future enhancements write zero 0 to all unused bits Table 3 26 Local Configuration and DMA Control Registers PCI Offset from Base Address Register Name Writable 00 07 Reserved N A 08 MARBR same as AC Y 0C Big Little Endian Descriptor Y 10 67 Reserved N A 68 INTCSR Y 70 Reserved N A 74 PCI H Rev Y 78 Reserved N A 80 DMA Channel 0 Mode Y 84 DMA Channel 0 PCI Address Y 88 DMA Channel 0 Lo...

Page 42: ... Reserved Yes No 1 31 26 Reserved Yes No 00 Table 3 28 Big Little Endian Descriptor Register BIGEND BAR0 1 Offset 0C Bit Description Read Write Value after PCI Reset 4 0 Reserved Yes No 00 5 PCI PIO RFM Address Space Big Endian Mode Address Invariance Writing a one 1 specifies use of Big Endian data ordering for PCI accesses to the RFM Address Space Writing a zero 0 specifies Little Endian orderin...

Page 43: ... 0 11 Local Interrupt Input Enable Writing a one 1 enables a local interrupt i e RFM interrupts to assert a host Interrupt Yes Yes 0 14 12 Reserved Yes No 0 15 Local Interrupt Input Active When set to a one 1 indicates the Local interrupt input is active Yes No 0 16 Reserved Yes No 1 17 Reserved Yes No 0 18 Local DMA Channel 0 Interrupt Enable Writing a one 1 enables DMA Channel 0 interrupts Clear...

Page 44: ...Width An 11 indicates a 32 bit bus width Yes No 11 6 2 Reserved Yes No 00 7 Continuous Burst Enable A one 1 enables Continuous Burst mode Yes No 1 8 Local Burst Enable A one 1 indicates Local Bursting Yes No 1 9 Scatter Gather Mode Writing one 1 indicates DMA Scatter Gather mode is enabled For Scatter Gather mode the DMA descriptors are loaded from memory in PCI Address space Writing zero 0 indica...

Page 45: ... Channel 0 Descriptor Location A one 1 indicates PCI Address space Yes No 1 2 1 Reserved N A N A 0 3 Direction of Transfer Writing a one 1 indicates transfer from the RFM to the PCI bus Writing a zero 0 indicates transfer from the PCI bus to the RFM Yes Yes 0 31 4 Channel 0 First Descriptor Address This field holds bits 31 4 of the first DMA descriptor address The first descriptor address must be ...

Page 46: ...Space Indicator A zero 0 indicates Local Address Space 1 maps into PCI Memory space Yes No 0 3 1 Reserved Yes No 0 31 4 Range Specifies which PCI Address bits to use for decoding a PCI access to Local Address Space 1 Each bit corresponds to a PCI Address bit Bit 31 corresponds to address bit 31 Write one 1 to all bits that must be included in decode and zero 0 to all others Used in conjunction wit...

Page 47: ...al Address Space 1 Base Address programmed in this register A Direct Slave access to an offset from PCIBAR3 maps to the same offset from this Local Base Address Yes Yes 0 NOTE Remap Address value must be a multiple of the LAS1RR range Table 3 41 PCI PIO Direct Slave Local Base Address Remap Continued LAS1BA BAR0 1 Offset F4 Bit Description Read Write Value after PCI Reset ...

Page 48: ...d 13 10 LISR Local Interrupt Status Reg read write Some bits reserved Some bits read only 17 14 LIER Local Interrupt Enable Reg read write 1B 18 NTD Network Target Data read write 32 Data bits for network target 1C NTN Network Target Node read write Target node ID for network Int 1D NIC Network Interrupt Command read write Select Int type and initiate interrupt 1F 1E Reserved 23 20 ISD1 Int 1 Send...

Page 49: ...ard on a network must have a unique node ID 3 3 5 Local Control and Status Register 1 Local Control and Status Register 1 LCSR1 BAR2 Offset 08 A 32 bit register containing Reflective Memory control and status bits is described below Table 3 43 Local Control and Status Register 1 LCSR1 BAR2 Offset 08 Bit 31 Bit 30 Bit 29 Bit 28 Bit 27 Bit 26 Bit 25 Bit 24 Status LED Transmitter Disable Dark on Dark...

Page 50: ...ional testing with or without an external cable Bit 27 Local Memory Parity Enable When this bit is set high 1 parity checking is enabled when reading from the RFM 5565 SDRAM Note that parity works only on 32 bit and 64 bit accesses Byte 8 bit Word 16 bit and 24 bit memory write accesses are inhibited while parity is enabled Bit 26 Redundant Mode Enabled When this bit is set high 1 redundant mode o...

Page 51: ... network Offset 1 and Offset 0 will apply an offset to the network address as it is sent or received over the network The offset does not appear on local access to the memory and the offset does not alter network packets as they pass through the board Offset 1 and Offset 0 provide four possible binary increments of 64 MBytes each through the 256 MByte network address range When the address and off...

Page 52: ...ived data may have been lost Bit 04 Latched RX FIFO Almost Full A logic high 1 indicates the RX FIFO is operating at the maximum acceptable rate Under normal operating conditions this event should not occur This bit is read only within this register To clear this condition write to the corresponding bit within the Local Interrupt Status Register Bit 03 Latched Sync Loss A logic high 1 indicates th...

Page 53: ...ntrolled by Bit 11 of the Local Configuration register INTCSR at offset 68 to Base address 0 The control and status of local interrupts are implemented in the two local registers LISR and LIER The bit functions of these two registers mirror each other Local Interrupt Status Register Local Interrupt Status Register LISR BAR2 Offset 10 This is a 32 bit register containing a group of interrupt status...

Page 54: ... bit and 64 bit accesses Word 16 bit and byte 8 bit memory write accesses are inhibited Bit 12 Memory Write Inhibited When this bit is high 1 an 8 bit byte a 16 bit word or a 24 bit write to local memory was attempted and inhibited while the board was in the parity enabled mode This bit is latched Once set it must be cleared by writing a zero to this bit location Bit 11 Latched Sync Loss When this...

Page 55: ... zero 0 to this bit location This is a fault condition and data may have been lost NOTE This condition should not occur during normal operation Bit 05 is for diagnostic purposes only Bit 04 Reserved This bit is reserved Bit 03 Reset Node Request When this bit is high 1 another node on the network has requested that the local PCI bus master reset this board The RFM 5565 does not reset itself automa...

Page 56: ...nterrupt Command Register as a single 16 bit word 3 3 9 Network Interrupt Command Register Network Interrupt Command NIC BAR2 Offset 1D An 8 bit register containing a four bit code that defines the type of network interrupt issued See Table 3 49 for a definition of the possible codes The NIC is both read and write accessible Only writing to the NIC register will initiate the network interrupt The ...

Page 57: ... node and if the network interrupt is of type 1 then the sender s node ID is stored in a 127 location deep FIFO called the Interrupt 1 Sender ID FIFO or SID1 Like any normal FIFO each time the SID1 is read the FIFO address pointer automatically increments to the next location in the FIFO Therefore each sender ID can only be read once from the SID1 FIFO Writing any data to the SID1 FIFO causes the ...

Page 58: ...oning just like ISD1 except it responds only to type 3 network interrupts 3 3 15 Interrupt 3 Sender ID FIFO Interrupt 3 Sender ID FIFO SID3 BAR2 Offset 34 An 8 bit FIFO functioning just like SID1 except it responds only to type 3 network interrupts 3 3 16 Interrupt 4 Sender Data FIFO Interrupt 4 Sender Data FIFO ISD4 BAR2 Offset 38 A 32 bit FIFO functioning just like ISD1 except it responds only t...

Page 59: ...etwork Interrupt 1 Data FIFO 127 Loc x 32 Bits Network Interrupt 2 Data FIFO 127 Loc x 32 Bits Network Interrupt 4 Sender ID FIFO 127 Loc x 8 Bits Network Interrupt 3 Data FIFO 127 Loc x 32 Bits Network Interrupt 4 Data FIFO 127 Loc x 32 Bits Interrupt Detection and Routing Circuitry PCI Interrupt Interface Read Address Pointer 1 Read Address Pointer 2 Read Address Pointer 3 Read Address Pointer 4...

Page 60: ...rupt is enabled the user software routine waits for the interrupt to occur 4 After the DMA is finished clear the DMA completion bit with a write to DMACSR0 as follows This is necessary when using DMA interrupts DMA channel 0 Command Status register DMACSR0 at PCIBAR0 offset A8 Write 8 to clear the DMA completion bit before attempting another DMA Table 3 50 DMA Registers DMA channel 0 mode setting ...

Page 61: ... boundary For best performance each descriptor block should be aligned on a 16 byte or 8 byte boundary A descriptor chain must be created in PCI 32 bit memory space before starting a Scatter Gather DMA Each descriptor in the chain has this format 1st Dword Lower 32 bit PCI Address for Data each page must be aligned on an 8 byte boundary 2nd Dword Upper 32 bit PCI Address for Data 0 for 32 bit addr...

Page 62: ...d Status register DMACSR0 at PCIBAR0 offset A8 Write 8 to clear the DMA completion bit before attempting another DMA Table 3 51 DMA Channel 0 Mode Settings DMA channel 0 mode setting Bit 9 set to 1 indicates the use of Scatter Gather DMA not normal Block mode DMAMODE0 at PCIBAR0 offset 80 DMA channel 0 PCI starting address This register is unused during Scatter Gather DMA DMAPADR0 at PCIBAR0 offse...

Page 63: ...he PCI memory window size The switch settings should only be changed while the power is off Use S1 switch positions 3 and 4 to select one of the four window sizes Bits 20 and 21 of RFM register LCSR1 PCIBAR2 Offset 08 indicate the full installed memory size Bit 19 of LCSR1 is connected to S1 switch position 3 and bit 22 of LCSR1 is connected to S1 switch position 4 Both bits 19 and 22 can be read ...

Page 64: ...FFF NOTE After writing a new value to the LAS1BA remap register the user application should read the LAS1BA remap register before accessing the new window This ensures the new window mapping has taken effect and subsequent memory accesses will be to the new memory window In summary register LAS1RR is the range register corresponding to the size of the PCI window and is read only Register LAS1BA is...

Page 65: ...d modify write operation if other sources in the LISR are to remain unchanged 7 Using a read modify write operation set Bit 8 and Bit 11 high 1 in the INTCSR register at PCIBAR0 offset 68 Bit 8 is the PCI Interrupt Enable and Bit 11 is the Local Interrupt Input LINTi Enable 3 7 2 Servicing Network Interrupts Read the INTCSR register at PCIBAR0 offset 68 Verify that the Local Interrupt Input Active...

Page 66: ...NTENTS ARE PROVIDED AS IS WITH NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED INCLUDING BUT NOT LIMITED TO WARRANTIES OF DESIGN MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE ALL OTHER LIABILITY ARISING FROM RELIANCE ON ANY INFORMATION CONTAINED HEREIN IS EXPRESSLY DISCLAIMED Abaco Systems Information Centers Americas 1 866 652 2226 866 OK ABACO or 1 256 880 0444 Inte...

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