38 PCI-5565PIORC* Ultrahigh Speed Fiber-Optic Reflective Memory with Interrupts
Publication No. 500-9367855565-000 Rev. D.0
PCI Base Address Register 3 contains the starting address for PIO memory
mapped accesses to the Reflective Memory RAM. The value in this register is
loaded by the system BIOS. It depends on both the amount of installed SDRAM
and the settings of S1 switch positions 3 and 4. The address offset range is:
$0 to $01FFFFF for the 2-MByte window setting,
$0 to $0FFFFFF for the 16-MByte window setting,
$0 to $3FFFFFF for the 64-MByte window setting,
$0 to $7FFFFFF for the 128-MByte SDRAM option, and
$0 to $FFFFFFF for the 256-MByte option.
NOTE
While examining the contents of the PCI Configuration Registers, the user may notice that Base Address
Register 4 contains a non-zero value and may mistakenly believe that this value specifies a set of useful
functions. Actually the registers within Base Address Register 4 are a set of special diagnostic registers
for the PLD Applications PCI-X core. These registers should be considered reserved and remain
unaltered by the user.
Table 3-14 PCI Base Address Register 3 for Access to Reflective Memory
PCIBAR3: Offset $1C
Bit
Description
Read
Write
*Value after
PCI Reset
0
Memory Space Indicator
. Writing zero (0) indicates the
register maps into Memory Space. Writing a one (1)
indicates the register maps into I/O Space.
Yes
No
0
2:1
Register Location
. Values:
00 - Locate anywhere in 32-bit Memory Address Space.
01 - Locate below 1-MByte Memory Address Space.
10 - Locate anywhere in 64-bit Memory Address Space.
11 - Reserved
If I/O Space, Bit 1 is always 0 and Bit 2 is included in
the base address.
Yes
Mem: No I/
O
Bit 1 no,
Bit 2 yes
00
3
Prefetchable
(If Memory Space).
Writing a one (1) indicates there are no side effects on
reads. Does not affect operation of the Reflective
Memory. The associated Bus Region Descriptor
register controls prefetching functions of this address
space. If I/O Space, Bit 3 is included in the base
address.
Yes
Mem: No
I/O: Yes
0
31:4
Memory Base Address
. Memory Base Address for
access to SDRAM.
Yes
Yes
$0
*
NOTE:
This register will be altered by the system BIOS during the system boot process.
Table 3-15 PCI Base Address Register 4
PCIBAR4: Offset $20
Bit
Description
Read
Write
Value after
PCI Reset
31:0
Reserved.
Yes
No
$0