Aaeon VIA Eden Series, User Manual

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88 Gene-6310 User Manual
Programming the watchdog timer
An on-board watchdog timer reduces the chance of disruptions
which CPLD (compact programmable logical device) interference
can cause. This is an invaluable protective device for standalone or
unmanned applications. When the watchdog timer activates(CPU
processing has come to a halt), it can reset the system, or generate
an interrupt on IRQ10, IRQ11, IRQ15, and NMI. This can be set via
I/O Port 444, the functions as following:
0 : RESET
1 : NMI
2 : IRQ10
3 : IRQ11
4 : IRQ15
If you decide to program the watchdog timer, you must write data
to I/O port 443 (hex). The output data is a value timer. You can
write from 0
1 (hex) to FF (hex) for input second data, and the related
timer is 1 to 255 seconds.
After data entry, your program must refresh the watchdog timer by
rewriting the I/O port 443 (hex) while simultaneously setting it.
When you want to disable the watchdog timer, your program
should read a Hex value from I/O port 80 (hex) .