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E m b e d d e d B o x
T K S - G 2 1 - C V 0 5
Appendix A Programming the Watchdog Timer
A-2
A.1 Programming
TKS-G21-CV05 utilizes ITE 8783 chipset as its
watchdog timer controller. Below are the procedures to complete
its configuration and the AAEON initial watchdog timer
program is also attached based on which you can
develop customized program to fit your application.
Configuring Sequence Description
After the hardware reset or power-on reset, the ITE 8783 enters the
normal mode with all logical devices disabled except
KBC. The initial state (enable bit ) of this logical device (KBC) is
determined by the state of pin 121 (DTR1#) at the falling edge of
the system reset during power-on reset.
Summary of Contents for TKS-G21-CV05
Page 18: ...Embedded Box T K S G 2 1 C V 0 5 Chapter 2 Quick Installation Guide 2 4 Solder Side...
Page 32: ...Embedded Box T K S G 2 1 C V 0 5 Chapter 3 AMI BIOS Setup 3 1 AMI Chapter 3 BIOS Setup...
Page 50: ...Embedded Box T K S G 2 1 C V 0 5 Appendix B I O Information B 1 I O Information Appendix B...
Page 51: ...Embedded Box T K S G 2 1 C V 0 5 Appendix B I O Information B 2 B 1 I O Address Map...
Page 52: ...Embedded Box T K S G 2 1 C V 0 5 Appendix B I O Information B 3...
Page 53: ...Embedded Box T K S G 2 1 C V 0 5 Appendix B I O Information B 4 B 2 1st MB Memory Address Map...
Page 54: ...Embedded Box T K S G 2 1 C V 0 5 Appendix B I O Information B 5 B 3 IRQ Mapping Chart...
Page 55: ...Embedded Box T K S G 2 1 C V 0 5 Appendix B I O Information B 6 B 4 DMA Channel Assignments...
Page 56: ...Embedded Box T K S G 2 1 C V 0 5 Appendix C AHCI Setting C 1 AHCI Setting Appendix C...
Page 58: ...Embedded Box T K S G 2 1 C V 0 5 Appendix C AHCI Setting C 3 Step 3 Setup OS Step 4 Press F6...
Page 61: ...Embedded Box T K S G 2 1 C V 0 5 Appendix D Digital I O D 1 Digital I O Appendix D...