Aaeon PCM-7890, User Manual

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64 PCM-7890 User Manual
EDO RASx# Wait State
The board designer may elect to insert one additional wait state
before RAS# is asserted for row misses, thus allowing one addi-
tional MAX[13:0] setup time to RASx# assertion. This field applies
only if EDO DRAM is installed in the system.
SDRAM RAS-to-CAS Delay
This field lets you control the number of DCLKs between a Row
Activate command and a read or write command.
SDRAM RAS Precharge Time
The precharge time is the number of cycles it takes for the RAS to
accumulate its charge before DRAM refresh. If insufficient time is
allowed, refresh may be incomplete and the DRAM may fail to
retain data. This field applies only if synchronous DRAM is
installed in the system.
SDRAM CAS Latency Time
When synchronous DRAM is installed, you can control the
number of CLKs between when the SDRAMs sample a read
command and when the contoller samples read data from the
SDRAMs. Do not reset this field from the default value specified
by the system designer.
SDRAM Precharge Control
When Enabled, all CPU cycles to SDRAM result in an All Banks
Precharge Command on the SDRAM interface.
DRAM Data Integrity Mode
Select Non-ECC or ECC (error-correcting code), according to the
type of installed DRAM.
System BIOS Cacheable
Selecting Enabled allows caching of the system BIOS ROM at
F0000h-FFFFFh, resulting in better system performance. However,
if any program writes to this memory area, a system error may
result.