H a l f - s i z e S B C
H S B - 9 6 5 P
Appendix A Programming the Watchdog Timer
A-4
Bit Description
7-2 Reserved
1
Returns to the Wait for Key state. This bit is used when the
configuration sequence is completed.
0
Resets all logical devices and restores configuration registers
to their power-on states.
WatchDog Timer Control Register (Index=71h, Default=00h)
Bit Description
7
WDT is reset upon a CIR interrupt
6
WDT is reset upon a KBC (Mouse) interrupt
5
WDT is reset upon a KBC (Keyboard) interrupt
4
WDT is reset upon a read or a write to the Game port base
address
3-2 Reserved
1
Force Time-out. This bit is self-clearing
0 WDT
status
1: WDT value reaches 0
0: WDT value is not 0
WatchDog Timer Configuration Register (Index=72h,
Default=00h)
Bit Description
7
WDT Time-out value select
1:
Second
0:
Minute
6
WDT output through KRST (pulse) enable
5
WDT Time-out value Extra select
1: 4s.
0: Determine by WDT Time-out value select (bit7 of this
register)
4
WDT output through PWROK1/PWROK2 (pulse) enable
3
Select the interrupt level
note
for WDT
Summary of Contents for HSB-965P
Page 7: ...Half size SBC H S B 9 6 5 P Chapter 1 General Information 1 1 General Chapter 1 Information...
Page 16: ...Half size SBC H S B 9 6 5 P Solder Side Chapter 2 Quick Installation Guide 2 4...
Page 18: ...Half size SBC H S B 9 6 5 P Chapter 2 Quick Installation Guide 2 6 Solder Side...
Page 30: ...Half size SBC H S B 9 6 5 P Chapter 3 Award BIOS Setup 3 1 Chapter Award 3 BIOS Setup...
Page 34: ...Half size SBC H S B 9 6 5 P Chapter 4 Driver Installation 4 1 Chapter Driver 4 Installation...
Page 48: ...Half size SBC H S B 9 6 5 P Appendix B I O Information B 1 I O Information Appendix B...
Page 49: ...Half size SBC H S B 9 6 5 P Appendix B I O Information B 2 B 1 I O Address Map...
Page 50: ...Half size SBC H S B 9 6 5 P Appendix B I O Information B 3 B 2 Memory Address Map...
Page 52: ...Half size SBC H S B 9 6 5 P Appendix C Mating Connector C 1 Mating Connector x Appendi C...