Aaeon HSB-800I-A11, User Manual

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Chapter 3 – AMI BIOS Setup 33
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3.5 Advanced Chipset Features
DRAM Timing Selectable [Default: By SPD]
When select to “By SPD”, the DRAM timing parameters are set according to DRAM SPD
(Serial Presence Detect). When disabled, one can manually set the DRAM timing
parameters through the sub items below. Set to “By SPD” if not sure.
CAS Latency Time: [Default: 2]
Controls the latency between the SDRAM Read command and the time data actually
becomes available.
Active to Precharge Delay: [Default: 8]
Delay between DRAM Activate Command to Precharge Command
DRAM RAS# to CAS# Delay [Default: 4]
Controls the latency between the DDR SDRAM active command and the read/write
command.
DRAM RAS# Precharge [Default: 3]
Controls the idle clocks after issuing a precharge command to the DDR SDRAM.
DRAM Data Integrity Mode [Default: Non-ECC]
Select Parity or ECC (error-correcting code), according to the type of installed DRAM.
Memory Frequency For [Default: Auto]
Allows you to set the DDR operating frequency.