4DSP FMC204, User Manual

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UM008 FMC204 User Manual
r1.14
UM008 www.4dsp.com - 26 -
Field Description
DIRx Direction of Front IO transceiver (x = 0 to 3)
‘0’
Signal x is input (FMC204 is receiver)
‘1’
Signal x is output (FMC204 is transmitter)
FANx Power control for FAN header (x = 0 to 3)
‘0‘
Apply power to FAN header x
‘1‘
Cut power to FAN header x
Table 13: Register CPLD_REG1 description
Bit nr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name
Reserved IRQ VM STATUS LD
REFMON
Table 14: Register CPLD_REG2 definition (read)
Field Description
REFMON Reflect the status of the REFMON output of the AD9517
LD Reflect the status of the LD output of the AD9517
STATUS Reflect the status of the STATUS output of the AD9517
VM
Reflect the status of the INT# output of the ADT7411 (inverted)
‘0‘
INT# is not asserted
‘1‘
INT# is asserted, access to the ADT7411 trough the I
2
C bus is required to
determine the source of the interrupt
IRQ Logic function: NOT (REFMON AND LD AND STATUS AND INT#)
‘0‘
All status signals indicate OK
‘1‘
One or more status signals indicate ERROR
Table 15: Register CPLD_REG2 description (read)
Bit nr. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
Name Reserved LED_SEL
Table 16: Register CPLD_REG2 definition (write)