UM027 FC6301 User Manual
r1.3
UM027
www.4dsp.com
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Virtex-6
FPGA
50MHz
crystal
CPLD
VITA 57.1
FMC
CDCV304
Clock
synthesizer
CDCEL925
PCIe-PCI
bridge
100MHz
Low jitter
LVDS
Jitter
attenuator
and buffer
MGT
FMC ref CLK
MGT
16 MHz
crystal
cPCI clock
33/66 MHz
Figure 5 : Clock tree
4.8.1 FMC GTX Reference Clock
The FMC standard defines two high precision reference clocks that are driven from the FMC
to the carrier. The FC6301 connects these clocks directly to GTX reference clock inputs. The
following table shows which GTX/GTHs can use these reference clocks.
FPGA Pin
Net name
GTX REFCLK
GTX/GTHs reached
AK7
GBTCLK0_M2C_n
GTXREFCLK0_112
112, 113
AK8
GBTCLK0_M2C_p
AD7
GBTCLK1_M2C_n
GTXREFCLK1_113
112, 113,114
AD8
GBTCLK1_M2C_p
Table 11: FMC GTX reference clock connections
4.8.2 FMC Clock connections
The FMC clocks are connected to LVDS capable I/O on the FPGA. CLK0 and CLK1 are
connected to global clock inputs. CLK2 and CLK3 are connected to regular I/O.
FPGA Pin
Net Name
FMC HPC
Pin Number
Pin Name
AN13
CLK0_M2C_n
H5
CLK0_M2C_N
AN14
CLK0_M2C_p
H4
CLK0_M2C_P
AY13
CLK1_M2C_n
G3
CLK1_M2C_N
AY14
CLK1_M2C_p
G2
CLK1_M2C_P
AM12
CLK2_BIDIR_n
K5
CLK2_BIDIR_N
AM13
CLK2_BIDIR_p
K4
CLK2_BIDIR_P
AW16
CLK3_BIDIR_n
J3
CLK3_BIDIR_N
AV16
CLK3_BIDIR_p
J2
CLK3_BIDIR_P
Table 12: FMC clock connections
