Hardware Development Guide of Module Product
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MF206A
3.11.2
Application of JTAG Interface
On the system board, you need to reserve the testing point or interface of the related JTAG signal, so as to solve
the un-repairable fault of LGA module due to emergencies such as downloading interruption.
3.12
Power-on/Power-off & Reset Signal
3.12.1
Description of PINs
To turn on the module the pad POWER_ON must be tied low for at least 0.05 seconds and then released.
To turn off the module the pad POWER_ON must be tied low for at least 5 seconds and then released.
A simple circuit to do it is as shown in the following Figure 3-9.
NOTE:
The resistors R1 and R2 in Figure 3-9 and Figure 3-1 are only the recommended value and they may
different according to the users transistor selection.