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Страница 1: ...Z8 Microcomputer Technical Manual April 1983...

Страница 2: ...c...

Страница 3: ...Z8 Microcomputer Technical Manual n_...

Страница 4: ...ight 1983 by Zilog Inc All rights reserved No part of this publication may be reproduced without the written permission of Zilog Inc The information in this publication is subject to change without no...

Страница 5: ...1 Introduction 2 2 Address Spaces 2 3 Register File 2 3 1 Register Pointer 2 3 2 Instruction Set 2 3 3 Data Types 2 3 4 Addressing Modes 2 4 I O Operations 2 4 1 Timers 2 4 2 Interrupts 2 5 Oscillato...

Страница 6: ...tion Codes D Notation and Binary Encoding 5 4 1 Assembly Language Syntax 5 4 2 Condition Codes and Flag Settings 5 5 Instruction Summary 5 6 Instruction Descriptions and Formats Chapter 6 External Int...

Страница 7: ...Timing Z8681 Reset Conditions Z8682 Reset Conditions Chapter 8 Reset and Clock 8 1 Reset 8 2 Clock 8 3 Power down Operation 8 4 Test Mode 8 4 1 8 4 2 Interrupt Testing ROMless Operation Chapter 9 I O...

Страница 8: ...rces 10 3 Interrupt Request Register Logic and Timing 10 4 Interrupt Initialization 10 4 1 10 4 2 10 4 3 Interrupt Priority Register Initialization Interrupt Mask Register Initialization Interrupt Req...

Страница 9: ...Conditions Chapter 12 Serial I O 12 1 Introduction 12 2 Bit Rate Generation 12 3 Receiver Operation 12 4 12 5 12 3 1 Receiver Shift Register 12 3 2 Overwrites 12 3 3 Framing Errors 12 3 4 Parity Tran...

Страница 10: ...Pointer Stack Operations Register Addressing Working Register Addressing Indirect Register Addressing to Register File Indirect Register Addressing to Program or Data Memory Indexed Addressing Direct...

Страница 11: ...lator External Clock Interface Battery Backed Register Supply Normal and Test Mode Flow Voltage Waveform for Test Mode I O Port and Port Mode Registers Ports 0 1 and 2 Block Diagram Port 0 I O Operati...

Страница 12: ...11 18 Cascaded Counter Timers Figure 11 19 Counter Timer Reset Figure 11 20 Prescaler 1 Register Reset Figure 11 21 Prescaler 0 Reset Figure 11 22 Timer Mode Register Reset Figure 12 1 Figure 12 2 Fig...

Страница 13: ...Table 9 1 Table 10 1 Table 10 2 Table 12 1 Z8 Family of Products Condition Codes Control and Peripheral Register Reset Values Port 3 Line Functions Interrupt Types Sources and Vectors Interrupt Priori...

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Страница 15: ...stems development both hardware and software prototyping field trials pre production and full production For prototyping and preproduc tion or where code flexibility is important the ZS603 13 Protopac...

Страница 16: ...1 1 ZB Family of Products ROM Part Capacity Progr able Dedicated PCB Product Ntnber Bytes I O Pins I O Pins Footprint Conments 2K ROM Z8601 2K 32 4 ports 8 Power 40 Pin Masked ROM part used Control p...

Страница 17: ...ts Ports 0 1 2 3 can be programmed as input output or additional address lines The I O ports can also be programmed to provide timing status signals interrupt inputs and serial or parallel I O with or...

Страница 18: ...yte register file on board UART and two coun ter timers are provided Pin descriptions and fund ions are t he same as those for the Z8601 11 basic microcomputer Chapter 6 1 4 1 7 ROHlESS MICROCOMPUTER...

Страница 19: ...perate on the data before output to the printing mechanism I alll y VV L V o Disk Disk operations are read or write with input received from either the disk or the compu ter Data is transferred to the...

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Страница 21: ...nternal and external Data memory external Register file internal A maximum of 64K bytes of program memory are directly addressable In the Z8601 and Z8611 microcomputers internal program memory consist...

Страница 22: ...ion and a Swap instruction Decimal Adjust is used after a binary addition or subtraction on BCD digits 2 2 Logical Shift Rotate and Load instructions oper ate on bytes in the register file Bytes in da...

Страница 23: ...ntain the contents of the register file with a low power battery Architectural Overview 2 6 PROTOPACK The lB Protopack allows the user to prototype system hardware and develop software that is eventua...

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Страница 25: ...241 240 127 4 2 STACK POINTER BITS 7 0 STACK POINTER BITS 15 8 REGISTER POINTER PROGRAM CONTROL FlAGS INTERRUPT MASK REGISTER INTERRUPT REOUEST REGISTER INTERRUPT PRIORITY REGISTER PORTS 0 1 MODE PORT...

Страница 26: ...ter thus forming an 8 bit address Figure 3 4 illustrates this opera tion Since working registers are typically specified by short format instructions there are fewer bytes of code needed which reduces...

Страница 27: ...ers PO P3 are registers The functions and applications of control and peripheral registers are described in subsequent sections of this manual Address Spaces 3 4 CPU PROGRAM MEMORY The ZS can access...

Страница 28: ...AL ROM OR RAM IR05 IR05 JP IR04 IR04 JP IR03 IR03 JP IR02 IR02 JP IR01 IR01 JP IROO IROO JP NOT ADDRESSABLE Figure 3 5d Z8682 Program Memory Map When an interrupt occurs the address stored in the inte...

Страница 29: ...2 bit and 16 bit addresses External data memory can be included with or sep arated from the external program memory addressing space When data memory is separated from program memory the Data Memory o...

Страница 30: ...on The stack address always points to the data stored on the top of stack The Z8 stack is a return stack for Call instructions and interrupts as well as a data stack During a Call instruction the cont...

Страница 31: ...bit values or memory addresses A register pair must be speci fied as an even numbered address in the range 0 2 14 Addressing modes are instruction specific Section 5 4 discusses each addressing mode a...

Страница 32: ...onvention When accessing program memory or external data memory register pairs or working register pairs are used to hold the 16 bit addresses 8 BIT REGISTER FILE ADDRESS PROGRAM MEMORY REGISTER FILE...

Страница 33: ...ess of the next instruction to be executed The PC prior to the add consists of the address of the instruction following the Jump Relative JR or Decrement and Jump if Nonzero DJNZ instruction JR and DJ...

Страница 34: ...indicate a reg ister or memory address as the source operand the operand value used by the instruction is the value supplied in the operand field itself Because an immediate operand is part of the in...

Страница 35: ...BC dst src Subtract With Carry SUB dst src Subtract Chapter 5 Instruction Set Logical Instructions Mnemonic Operands AND dst src COM dst OR dst src Instruction Logical And Complement Logical Or XOR ds...

Страница 36: ...ag is set to 1 whenever the result of an arithmet ic operation generates a carry out of or a borrow into the high order bit 7 otherwise the Carry flag is cleared to O Following Rotate and Shift instru...

Страница 37: ...carry out of bit 3 Overflow or a subtraction generates a borrow into bit 3 The Half carry flag is used by the Decimal Adjust DA instruction to convert the binary result of a pre vious addition or subt...

Страница 38: ...ires that dst src be specified in that order The following instruction descriptions show the format of the object code produced by the assembler This binary format should be followed by users who pref...

Страница 39: ...I Minus S 0100 OV Overflow V 1100 NOV No overflow V 0 0110 EQ Equal Z 1 1110 NE Not equal Z 0 1001 GE Greater than or S XOR V 0 equal 0001 LT Less than S XOR V 1 1010 GT Greater Than Z OR S XOR V O 00...

Страница 40: ...127 128 SRA dst lE I DO 0 EI 9F Dl IMR 7 I SRP src 1m 31 INC dst rE RP src dst dst 1 r O F SUB dst src Note I 20 I R 20 dst dst src IR 21 SWAP dst R FO X X INCW dst RR AO IR FI dst dst IR Al TCM dst s...

Страница 41: ...addition of high order operands C Set if there is a carry from the most significant bit of the result cleared otherwise Z Set if the result is zero cleared otherwise 5 Set if the result is negative c...

Страница 42: ...rom the most significant bit of the result cleared otherwise Z Set if the result is zero cleared otherwise V Set if arithmetic overflow occurs that is if both operands are of the same sign and the res...

Страница 43: ...corresponding bits in the two operands are both 1s otherwise a 0 bit is stored The contents of the source bit are not affected C Unaffected Z Set if the result is zero cleared otherwise V Always reset...

Страница 44: ...ints to the first instruction of a procedure At the end of the procedure a R Turn instruction can be used to return to the original program flow RET pops the top of the stack back into the PC No flags...

Страница 45: ...Exmnple C NOT C CCF Complement Carry Flag Cycles 6 OPC Hex EF The C flag is complemented if C 1 it is changed to C 0 and vice versa C Complemented No other flags affected Tf the C flag contains a 0 th...

Страница 46: ...__ 6 BO B1 R IR Operation Flags Exmnple Note 5 12 dst 0 The destination location is cleared to O No flags affected If working register 6 contains AF the statement CLR R6 will leave the value 0 in that...

Страница 47: ...bits are changed to 0 and vice versa C Unaffected Z Set if the result is zero cleared otherwise V Always reset to 0 5 Set if result bit 7 is set cleared otherwise H Unaffected D Unaffected If working...

Страница 48: ...C Cleared if there is a carry from the most significant bit of the result set otherwise indicating a borrow Z Set if the result is zero cleared otherwise V Set if arithmetic overflow occurs cleared ot...

Страница 49: ...Carry Instruction Before DA Hex Before DA Hex To Byte After DA 0 0 9 0 0 9 00 0 0 0 8 0 A F 06 0 ADD 0 0 9 1 0 3 06 0 ADC 0 A F 0 0 9 60 1 0 9 F 0 A F 66 1 0 A F 1 0 3 66 1 1 0 2 0 0 9 60 1 1 0 2 0 A...

Страница 50: ...ed in the destination location using standard binary arithmetic 0001 0101 0010 0111 0Ul1 T11iU 3C The DA statement adjusts this result so that the correct BCD representation is obtained 0011 1100 0000...

Страница 51: ...one c Unaffected Z Set if the result is zero cleared otherwise V Set if arithmetic overflow occurred cleared otherwise 5 Set if the result is negative cleared otherwise H Unaffected D Unaffected If wo...

Страница 52: ...lue which is decremented by one C Unaffected Z Set if the result is zero cleared otherwise V Set if arithmetic overflow occurred cleared otherwise 5 Set if the result is negative cleared otherwise H U...

Страница 53: ...is reset to O All interrupts are disabled although they remain potentially enabled i e the Global Interrupt Enable is cleared not the individual interrupt level enables No flags affected If control re...

Страница 54: ...is the address of the instruction byte following the DJNZ statement When the working register counter reaches zero control falls through to the statement following DJNZ No flags affected DJNZ is typi...

Страница 55: ...er 251 the Interrupt Mask Register is set 10 to 1 This allows any potentially enabled interrupts to become enabled No flaqs affected If control register 251 contains OA 00001010 that is interrupts IRQ...

Страница 56: ...e incremented by one C Unaffected Z Set if the result is zero cleared otherwise V Set if arithmetic overflow occurred cleared otherwise S Set if the result is negative cleared otherwise H Unaffected 0...

Страница 57: ...incremented by one C Unaffected Z Set if the result is zero cleared otherwise V Set if arithmetic overflow occurred cleared otherwise S Set if the result is negative cleared otherwise H Unaffected 0...

Страница 58: ...SP 2 IMR 7 1 Cycles 16 ope Hex SF This instruction is issued at the end of an interrupt service routine It restores the Flag reqister control register 252 and the PC It also reenables any interrupts...

Страница 59: ...wing the JP instruction is executed See Section 6 4 for a list of condition codes The unconditional jump simply replsces the contents of the Program Counter with the contents of the specified register...

Страница 60: ...See Section 5 3 for a list of condition codes The range of the relative address is 127 128 and the original value of the PC is taken to be the address of the first instruction byte following the JR st...

Страница 61: ...on Flags Example Note dst src The contents of the source are loaded into the destination source are not affected No flags affected The contents of the If working register 0 contains OB 11 decimal and...

Страница 62: ...s used to load a byte constant from program memory into a working register or vice versa The address of the program memory location is specified by a working register pair The contents of the source a...

Страница 63: ...king register pair and the address of the register file location is specified by a working register The contents of the source location are loaded into the destination location Both addresses are then...

Страница 64: ...5 30 dst src This instruction is used to load a byte from external data memory into a working register or vice versa The address of the external data memory location is specified by a working registe...

Страница 65: ...ed by a working register pair and the address of the register file location is specified by a working register The contents of the source location are loaded into the destination location Both address...

Страница 66: ...NOP No Operation NlF Instruction format ope Operation flags 5 32 Cycles 6 OPC Hex FF No action is performed by this instruction It is typically used for timing delays No flags affected...

Страница 67: ...results in a one bit being stored whenever either of the corresponding bits in the two operands is 1 otherwise a 0 bit is stored C Unaffected Z Set if result is zero cleared otherwise V Always reset t...

Страница 68: ...oaded into the destination The SP is then incremented automatically No flags affected If the SP control registers 254 255 contains 1000 external data memory location 1000 contains 55 and working regis...

Страница 69: ...nts of the SP are decremented then the contents of the source are loaded into the location addressed by the decremented SP thus adding a new element to the top of the stack No flags affected If the SP...

Страница 70: ...ReF Reset Carry Flag ReF Instruction For at Cycles ope 6 Operation e 0 The e flag is reset to 0 regardless of ita previous value Flags c Reset to 0 No other flags affected 5 36 OPC Hex eF...

Страница 71: ...L instruction The contents of the location addressed by the SP are popped into the PC The next statement executed is that addressed by the new contents of the PC No flags affected If the PC contains 3...

Страница 72: ...rom the roost significant bit position was 1 i e bit 7 was 1 Z Set if the result is zero cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during r...

Страница 73: ...t if the bit rotated from the most significant bit position was 1 i e bit 7 was 1 Z Set if the result is zero cleared otherwise V Set if arithmetic overflow occurs that is if the sign of the destinati...

Страница 74: ...nificant bit position was 1 Le bit 0 was 1 Z Set if the result is zero cleared otherwise V Set if arithmetic overflow occurred that is if the sign of the destination changed during rotation cleared ot...

Страница 75: ...rotated from the least significant bit position was 1 i e bit 0 was 1 Z Set if the result is zero cleared otherwise V Set if arithmetic overflow occurred that is the sign of the destination changed du...

Страница 76: ...on of high order operands C Cleared if there is a carry from the most significant bit of the result set otherwise indicating a borrow Z Set if the result is 0 cleared otherwise V Set if arithmetic ove...

Страница 77: ...SCf Instruction format Cycles ope 6 Operation e 1 The e flag is set to 1 regardless of its previous value flags c Set to 1 No other flags affected SCF Set Carry Flag OPC Hex DF 5 43...

Страница 78: ...d and its value is also shifted into bit position 6 7 o c Set if the bit shifted from the least significant bit position was 1 i e bit 0 was 1 Z Set if the result is zero cleared otherwise V Always re...

Страница 79: ...ter group The working register group starting addresses are Hex Decimal 00 0 10 16 20 32 30 48 40 64 50 80 60 96 70 112 FO 240 control and peripheral registers Values in the range 80 EO are invalid No...

Страница 80: ...ignificant bit of the result set otherwise indicating a borrow Z Set if the result is zero cleared otherwise V Set if arithmetic overflow occurred that is if the operands were of opposite signs and th...

Страница 81: ...are swapped C Undefined Z Set if the result is zero cleared otherwise V Undefined S Set if the result bit 7 is set cleared otherwise H Unaffected 0 Unaffected Suppose the register named BCD_nperands...

Страница 82: ...checked to determine the result When the TeM operation is complete the destination location still contains its original value C Unaffected Z Set if the result is zero cleared otherwise V Always reset...

Страница 83: ...ult When the TM operation is complete the destination location still contains its original value c Unaffected Z Set if the result is zero cleared otherwise V Always reset to 0 S Set if the result bit...

Страница 84: ...XCLUSIVE OR operation results in a one bit being stored whenever the corresponding bits in the operands are different otherwise a 0 bit is stored c Unaffected Z Set if the result is zero cleared other...

Страница 85: ...m Port 1 for each external memory transfer During a Write cycle data out is valid at the leading edge of OS During a Read cycle data in must be valid prior to the trailing edge of OS 55 can be placed...

Страница 86: ...llowing access to 256 bytes of external memory In this configuration the eight lower order address bits AO A7 are multiplexed with the data DO D7 Port 0 can be programmed to provide four addi tional a...

Страница 87: ...should not be immediately followed by the instructions RET or IRET because this will cause indeterminate program flow 3047 002 3047 003 External Interface ZS601 ZS611 6 5 DATA I tI1RY The two external...

Страница 88: ...es that valid data is on the Port 1 ADO AD7 lines For Read operations R W High the Address Data bus is placed in a high impedance state before driving DS L6 so that the addressed device can put its da...

Страница 89: ...e common resources with other bus masters This shared bus mode is under software control and is programmed by setting Port 0 1 Mode register bits D4 and D3 both to 1 Figure 6 7 Data transfers can be c...

Страница 90: ...setting bit DS in the Port 0 1 Mode register to 1 Figure 6 8 Figures 6 9a and 6 9b illustrate extended memory Read and Write cycles R248 P01M Port 0 1 Mode Register F8 Write Only EXTERNAL MEMORY TlMI...

Страница 91: ...cycles have the same machine timing regardless of whether memory is internal or exter nal For those instructions that require execu tion time longer then that of the overlapped fetch or instructions...

Страница 92: ...STORE FETCH 1 FETCH 2 EXECUTION CYCLE II OPERAND INSTRUCTION INSTRUCTION FETCH ES ALU STORE FETCH 1 FETCH 2 EXECUTION CYCLE II INSTRUCTION INSTRUCTION FETCH 1 FETCH 2 EFFECTIVE _I HIDDEN DELAY I EXEC...

Страница 93: ...N I I Figure 6 11 Instruction Cycle Timing One Byte Instructions Ml M2 Ml OR M3 r T1 1 r T3 I Tl T2 T3 T2 r T3 CLOCK PO ______ X Aa A15 X Aa A15 X Aa A15 P1 X Ao A7 s Ao A7 Ao A7 AS OS I R W FETCH 3RD...

Страница 94: ...alues reset into P01M 6 10 R248 P01M Port 0 1 Mode Register F8 Write Only P04 P07 MODE OUTPUT 00 INPUT 01 A12 A15 1X EXTERNAL MEMORY TIMING NORMAL 0 EXTENDED 1 I P08oP U T 01 INPUT 1X As All STACK SEL...

Страница 95: ...ta Strobe provides the timing for data movement to or from Port 1 for each memory transfer During a Write cycle data out is valid at the leading edge of 55 During a Read cycle data in must be valid pr...

Страница 96: ...ammed to provide either four additional address lines A8 A11 which increases the addressable memory to 4K bytes or eight additional address lines A8 A15 which increases the addressable memory to 64K b...

Страница 97: ...ter F8 Write Only P04 P01 MODEI OUTPUT 00 r POa P03 MODE L 00 OUTPUT 01 INPUT 1X As All INPUT 01 A12 A15 1X Figure 7 5 Z8681 Port 0 Memory Operation The lower nibble of Port 0 can be defined as addres...

Страница 98: ...7 4 EXTERNAL STACKS The l8681 82 architecture supports stack opera tions in either the register file or data memory A stack s location is determined by bit D2 in the Port 0 1 Mode register For exampl...

Страница 99: ...e of AS indicates that R W OM if used and the addresses output from Ports 0 and 1 are valid The addresses output via Port 1 remain valid only during MnT1 and typically need to be latched using AS wher...

Страница 100: ...hardware reset Port 0 is configured as input port extended timing is set to accommodate slow memory access during the configuration routine DM is inactive and the stack resides in the register file Fi...

Страница 101: ...d Peripheral Register Reset Values Register FO Serial I O F1 Timer Mode F2 Counter Timer F3 f1 Prescaler F4 Counter Timer a F5 TO Prescaler F6 Port 2 Mode F7 Port 3 Mode F8 Port 0 1 Mode ZB601 ZB611 F...

Страница 102: ...nternal pull up combined with an external capacitor of 1 eF provides enough time to properly reset the Z8 Figure 8 2 R W Figure B 1 8 2 B 2 CLOCK The Z8 derives its timing from on board clock circuitr...

Страница 103: ...eneral purpose regis ters whenever VCC is removed During normal operation V MM provides 5 V along with VCC The following sequence is necessary to preserve data Power failure must be externally detecte...

Страница 104: ...ditional on board ROM is mapped into the first 64 locations of program memory Figure 8 7 shows the difference between Normal and Test modes of operation Test mode is entered by driving the RESET input...

Страница 105: ...lock 80C and 80F interrupt vectors in the Z8611 point to external memory locations 1000 1003 Q1006 1008 100C and 100F These interrupt vectors allow the external program to have a 2 or 3 byte JUMP inst...

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Страница 107: ...ts 9 1 2 Input and Output Registers Each bit of Ports 0 1 and 2 has an input regis ter an output register associated buffer and control logic Since there are separate input and output registers associ...

Страница 108: ...UT BUFFER A A K 8 K Ecf READ_r PORT INTERNAL TIMING HANDSHAKE SELECTED HANDSHAKE WRITE LOGIC PORT 8 J y Y OUTPUT ENABLE OUTPUT REGISTER OUTPUT BUFFER figure 9 2 Ports 0 1 and 2 Block Diagra 8 y I 8 PO...

Страница 109: ...or as outputs by setting both D6 and 07 to O 9 2 2 Handshake Operation When used as an I O port Port 0 can be placed under handshake control by programming the Port 3 Mode register bit 02 to 1 Figure...

Страница 110: ...ut strobe Using the Port 0 1 Mode register Port 1 is con figured as an output port by setting bits 04 and 0 3 to Os or as an input port by setting 04 to 0 and 03 to 1 Figure 9 6 R248 P01M Port 0 1 Mod...

Страница 111: ...drain output the data returned is the value forced on the output pin by the external system This may not be the same as the data in the output register Reading input bits of Port 2 also returns data...

Страница 112: ...ister for each bit Instead all the input lines have one input regis ter and output lines have an output register Under software control the lines can be con figured as input or output special control...

Страница 113: ...t 3 The special functions indicated in the table are discussed in detail in their corresponding sections in this manual Port 3 input lines P30 P33 always function as interrupt requests regardless of t...

Страница 114: ...Load P01 M or P2M to configure the port for input output Load P3 to set the Output Handshake bit to a logic 1 Load P3M to select the Handshake mode for the port Once a data transfer begins the configu...

Страница 115: ...us returning the in terface to its initial state Figure 9 16 zn Output Handshake l U Ports Figures 9 17 and 9 18 illustrate the strobed handshake connections 9 7 I O PORT RESET CONDITIONS A P2o P27 K...

Страница 116: ...R248 P01M Port 0 1 Mode Register F8 Write Only P04 P07 MODE OUTPUT 00 J INPUT 01 A12 A15 1X EXTERNAL MEMORY TIMING NORMAL 0 EXTENDED 1 c POO P03 MODE L 00 OUTPUT 01 INPUT 1X As All STACK SELECTION o...

Страница 117: ...e Only 0 01010101011101 I LoPORT 2 PULL UPS OPEN DRAIN 1 PORT 2 PULL UPS ACTIVE RESERVED o P32 INPUT P3s OUTPUT 1 P32 DAVO RDYO P3s RDYO DAVO o0 P33 INPUT P34 OUTPUT P33 INPUT P34 DM 1 1 P33 DAVlIRDY1...

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Страница 119: ...ts both vectored and polled interrupt handling Details on vectored and polled interrupts can be found in Sections 10 6 and 10 7 DEC HEX IDENTIFIERS 251 INTERRUPT MASK FB IMR 250 INTERRUPT REQUEST FA I...

Страница 120: ...nternal IRQ3 can be generated from an external source only if Serial In is not enabled otherwise its source is internal The ext ernal request is generated by a negative edge signal on P30 as shown in...

Страница 121: ...e before an opcode fetch Figure 10 6 External requests are sampled two internal clocks earlier due to the synchronizing flip flops shown in Figures 10 3 and 10 4 At sample time the request is transfer...

Страница 122: ...iority of the individual members within the three groups Bits DO 03 and 04 are encoded to define six priority orders between the three groups Bits 06 and 07 are not used R2491PR Interrupt Priority Reg...

Страница 123: ...BLES IR02 1 ENABLES IR03 1 ENABLES IR04 1 ENABLES IR05 1 ENABLES INTERRUPTS Figure 10 8 Interrupt Mask Register 3047 095 3047 064 Interrupts IRQ is held in a Reset state until an EI instruc tion is ex...

Страница 124: ...Cycle Tiaing Interrupt cycle timing for all Z8 devices except the Z8681 is diagrammed in Figure 10 12 Timing for the Z8681 ROMless device is different and is shown in Figure 10 13 10 6 2 Nesting of Ve...

Страница 125: ...t for request If no request go to NEXT If request is there then service it SERVICE Process Request AND IRQ IIMASK_ Clear Request bit RET Return to next In this example if IRQ2 is being polled MASK wil...

Страница 126: ..._ SERVICE ROUTINE L J _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ FOR STACK EXTERNAL ONLY Figure 10 12 ROM Z8 Interrupt T ing shrink parts l _ M3_ STACK PUSH_I_STACK PUSH_I_STACK PUSH I VE6 ii IGH_1 v...

Страница 127: ...r timer operates in either Single Pass or Continuous mode At the end of count counting either stops or the initial value is reloaded and counting continues Under software control new values are loaded...

Страница 128: ...trol bits that specify TO and T1 counting modes These bits also indicate whether the clock source for T1 is internal or external These control bits will be discussed in detail throughout this chapter...

Страница 129: ...2 machine state after the operand is fetched Figure 11 7 11 3 2 Prescaler Operations During counting the programmed clock source drives the prescaler 6 bit counter The counter is counted down from the...

Страница 130: ...counter timer value 1 256 It should be apparent that the prescaler and counter timer are true divide by n counters 11 4 TOUT MODES The Timer Mode register TMR F1 Figure 11 10 is used in conjunction w...

Страница 131: ...h to 1 The internal clock XTAL frequency 2 is then direct y output on P36 Figure 11 12 R241 TMR Timer Mode Register F1 Read Write TIN MODES EXTERNAL CLOCK INPUT 00 GATE INPUT 01 TRIGGER INPUT 10 NON R...

Страница 132: ...d disabled state of T1 IRQ2 must therefore be masked or enabled according to the needs of the application T N 1 P31 H D CLOCK IU1 i INTERNAL CLOCK 1 D j 11 5 1 External Clock Input Hode The TIN Extern...

Страница 133: ...2 OSC 2 P3l 0 0 f 4 r PREO INTERNAL CLOCK TMR 05 1 EDGE 4 TRIGGER 1 TMR 05 04 11 Figure 11 17 Triggered Clock Mode TO f 4 2 f P3s TOUT TIN Figure 11 18 Cascaded Counter Ti mers PRE1 T1 P3l H PRE1 L IR...

Страница 134: ...rated on every end of count 11 6 CASCADING COUNTER TIMERS For some applications it may be necessary to mea sure a time interval greater than a single coun ter timer can measure In this case TIN and TO...

Страница 135: ...e Register F1 Read Write 10101010101010101 TOUT MODES I TOUT OFF 00 To OUT 01 L0 NO FUNCTION 1 LOAD To T1 OUT 10 INTERNAL CLOCK OUT 11 TIN MODES EXTERNAL CLOCK INPUT 00 GATE INPUT 01 TRIGGER INPUT 10...

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Страница 137: ...are to access the serial I O as general purpose registers eliminating the need for special instructions 12 2 BIT RATE GENERATION When Port 3 Mode register bit D6 is set to 1 the serial I O is enabled...

Страница 138: ...r Mode register TMR F1 bits Dl and DO both to 1 Figure 12 6 This transfers the contents of the Prescaler and Counter Timer registers to their corresponding down counters In addition counting is enable...

Страница 139: ...the internal clock by two D type flip flops before being input to the Shift register and the start bit detection circuitry The ntart bit detection circuitry monitors the incoming data stream looking...

Страница 140: ...ead Received Oata No Parity 12 3 4 Parity The data format supported by the receiver must have a start bit eight data bits and at least one stop bit If parity is on bit 07 of the data received will be...

Страница 141: ...software to respond to IRQ4 appropriately I f polling is used the IRQ4 bit in the Interrupt Request regis ter must be reset 12 4 2 Parity The data format supported by the transmitter has a start bit e...

Страница 142: ...1 I ld 1 _____ SERIAL DATA Do LSB 12 6 Figure 12 11 Serial I O Register Reset R247 P3M Port 3 Mode Register F78 Write Only 1010101010101 101 L 0 PORT 2 PULL UPS OPEN DRAIN 1 PORT 2 PULL UPS ACTIVE oP...

Страница 143: ...A...

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Страница 145: ...ch Appendix A Pin Descriptions and Functions cycle when the first 4K bytes of program memory are being accessed SClK System Clock output SCLK is the inter nal clock output through a buffer The clock r...

Страница 146: ...POs P2s P07 P2s P27 P10 P11 P30 PORT 1 P12 P31 BYTE P13 P32 PROGRAMMABLE P14 Z8612 P33 PORT 3 1 0 OR ADo AD7 SERIAL AND PARALLEL P1s P34 1 0 CONTROL P1s P3s P17 P3s P37 Do D1 PROGRAM D2 A1 MEMORY D3 D...

Страница 147: ...P16 P03 15 50 Z8812 P1s Figure A J Protopack Emulator P04 16 49 P14 GNO 17 48 P13 POs 18 47 Ph SOCKET FOR 2716 EPROM 2732 EPROM P06 19 46 P11 21 P07 20 45 P10 lACK 21 44 07 DD SYNC 22 43 06 SCLK 23 42...

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Страница 149: ...B __ L 7 1 Zilog...

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Страница 151: ...CK SOURCE 1 T INTERNAL o T EXTERNAL TIMING INPUT T N MODE PRESCALER MODULO RANGE 1 64 DECIMAL 01 00 HEX R244 TO Counter Timer 0 Register F4H Read Write T INITIAL VALUE WHEN WRITTEN RANGE 1 256 DECIMAL...

Страница 152: ...OUP B C B A 101 o IRQ2 IRQO B A C 110 1 IRQO IRQ2 RESERVED 111 IRQ1 IRQ4 PRIORITY GROUP C o IRQl IRQ4 1 IRQ4 IRQl R250 IRQ Interrupt Request Register FAH Read Write I I I I I I I I I RESERVED T c IRQO...

Страница 153: ...c...

Страница 154: ......

Страница 155: ...IM IRI IM 6 5 10 5 10 5 10 5 10 5 SUB SUB SUB SUB SUB fl lr R RI IR RI Ri lM IRI IM f 6 5 10 5 10 5 10 5 10 5 SBC SBC SBC SBe SBe rl lr R RI IR RI Ri lM IRI IM f 6 5 10 5 10 5 la S 10 5 OR OR OR OR O...

Страница 156: ......

Страница 157: ...I...

Страница 158: ......

Страница 159: ...3 Control registers 3 3 B 1 Counter timers 1 1 1 3 1 4 2 2 11 1ff Cascaded 11 8 Continuous mode 11 1ff Enable Count bit 11 3 Load bit 11 3 Reset conditions 11 9 Index Counter Timers cont d Single Pass...

Страница 160: ...terface 6 1ff 7 1ff Handshake 9 3 Read Write 7 4 9 3 Port 0 1 Mode register P01M 3 3 3 6 6 2ff 7 3ff 9 3ff Port 1 1 4 9 4 Handshake 9 4 Read Write 9 4 Port 2 9 5 Handshake 9 5 Read Write 9 5 Port 2 Mo...

Страница 161: ...2 4 U UART Universal Asynchronous Receiver Transmitter 1 1 1 3 1 4 2 2 x XTAL1 XTAL2 Crystal 1 2 signals 6 2 z Zero flag Z see Flags Z8 Development Module OM 1 1 1 2 Z8 Emulator Z SCAN 8 1 1 1 2 Z8601...

Страница 162: ......

Страница 163: ...ware Model and Memory Size Describe your likes dislikes concerning this document Supporting Diagrams EaseofUse _____________________________________________________________ Your Name _________________...

Страница 164: ...SINESS REPLY MAIL FIRST CLASS PERMIT NO 35 CAMPBELL CA POSTAGE WILL BE PAID BY Zilog 1315 Dell Ave Campbell California 95008 ATTENTION Corporate Publications No Postage Necessary If Mailed In The Unit...

Страница 165: ......

Страница 166: ...stin TX 78757 Phone 512 453 3216 Zilog Inc 1315 Dell Ave Campbell California 95008 03 3047 03 East Sales Technical Center Zilog Incorporated Corporate Place 99 South Bedford S1 Burlington MA 01803 Pho...

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