User Manual
UM015201-0603
Peripheral Bus Connector
ZiLOG Development Platforms
eZ80
®
Sales Demonstration Platform
9
Figure 5. eZ80
®
Sales Demonstration Platform Peripheral Bus Connector Pin Configuration
Table 2. Peripheral Bus Connector Pin Identification (see Figure 5 for Pin #s)
Function
Pull
Up/Down*
Signal Direction
(with respect to
the Platform
board)
Description
A0 - A23
n/a
Bidirectional
24-bit address bus
D0 - D7
n/a
Bidirectional
8-bit data bus
TRSTN
OUT
Reset for On-Chip Instrumentation (OCI).
F91_WE
OUT
Low enables write to on-chip Flash memory.
If this pin is unconnected, on-chip Flash
memory is write-protected.
DIS_FLASH
OUT
External Flash Memory enable input.
CS0 - CS2
n/a
IN
Chip Selects for on-board or external devices
MREQ
Bidirectional
Bus Cycle Memory indication.
Notes: *External capacitive loads on RD, WR, IOREQ, MREQ, D0–D7 and A0–A23 must be below 10pF to
satisfy timing requirements for the eZ80® CPU. All unused inputs must be pulled to either V
DD
or
GND, depending on their inactive levels to reduce power consumption and to reduce noise sensitivity.
To prevent EMI, the EZ80CLK output can be deactivated by software in the eZ80F92 Peripheral
Power-Down Register. All inputs are CMOS level 3.3V (5V tolerant), except where otherwise noted.
A13
GND
A23
D4
-RD
-F91_WE
-MREQ
A17
GND
VCC_33V
-IOREQ
VCC_33V
D7
A12
A20
A8
-TRSTN
D2
A3
A10
D6
VCC_33V
A19
A0
A22
A14
A16
D1
A15
D5
A9
-CS0
A7
GND
D3
-WR
GND
D0
-BUSACK
A5
A21
A11
A1
A4
A18
A6
-CS1
-CS2
-INSTRD
A2
GND
-DIS_FLASH
-BUSREQ
J
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
JP1
