Page 3.5
System Input/Output
Table 3.1(continued). System Bus Signal Names
PIN
DEFINITION
SIGNAL
B5
B6
A25
A26
A27
A28
A29
A30
A31
Bl
B2
B3
B4
B7
B8
B9
BIO
Bll
B12
B13
B14
B15
B17
B16
B18
IOR*
IOW*
A7
A6
A5
A4
A3
A2
Al
AO
GND
RESET
+5 VDC
IRQ2
MEMR+
DACK3+
DRQ3
DACKI*
— 5 VDC
DRQ2
— 12 VDC
N.C.
+12 VDC
GND
MEMW+
Address bit 7
Address bit 6
Address bit 5
Address bit 4
Address bit 3
Address bit 2
Address bit I
Address bit 0
Ground
When high, resets or initializes system logic devices.
+ 5 VDC bus.
Interrupt request 2.
Not used.
Available for assignment to a user-selected device.
— 5 VDC bus.
DMA request 2.
Assigned to floppy disk controller.
— 12 VDC bus.
No connection.
+12 VDC bus.
Ground
Memory write.
When low, causes data on data bus to be stored
in memory.
Memory read.
When low, causes memory to drive data onto the
data bus.
I/O write.
When low, instructs an I/O device to read the
data on the data bus.
I/O read.
When low, instructs an VO device to drive its data
onto the data bus.
DMA acknowledge 3.
Assigned to the Winchester drive controller.
DMA request 3.
Assigned to the Winchester drive controller.
DMA acknowledge 1.
Not used.
Available for user assignment.
DMA request 1.
DRQI
Содержание Z-100 Series
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