1-2
OVERVIEW
1.1 Explanation
- HD PERSONAL VIDEO RECORDER & RECEIVER or PVR(Personal Video Recorder)-STB(Set-Top Box)
stores video and audio data into HDD with a specific form while receiving the ground wave of HD digital
broadcasting only or gives additional related services.
- Configuration
It uses IBM PPC405GP of PowerPC series as CPU, which supports PCI Bus I/F for PVR. VSB section exe-
cutes VSB decoding for ATSC signal with IF(44MHz) as an input entered from the tuner and transfers TP
data by decoding ATSC signal via VSB decoding to PVR section and HD-1.
MPEG Decoder supports MP@HL by using HD-1 and uses an external AC-3 Decoder.
PVR section stores only necessary data of TP data from the digital TV signal into HDD via IDE I/F chip.
The overall structure is as follows:
- System section
CPU, Main Memory, MPEG-II Decoder, AC-3 Decoder, Flash Memory, Audio DAC, CPLD
- PVR section
PCI I/F, PDR-Pro executing TP De-Mux, Memory, IDE I/F Chip
- VSB section
Generate TP signal by transferring the IF of the desired channel from the RF signal received from the tuner
to VSB receiver.
- Front section
Receive various user key inputs and display the status of the set-top box on the LED.
- Power section
Supply the DC power to the main digital board and HDD by using AC 120V as an input.
Содержание HDR230
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Страница 38: ...3 17 3 18 4 WAVEFORMS 1 DIGITAL SYSTEM CLOCK GENERATOR PART 1 2 3...
Страница 39: ...3 19 3 20 2 DIGITAL SYSTEM SYSTEM MEMORY PART 1 2 3...
Страница 40: ...3 21 3 22 3 VIDEO PLL PART 1 2...
Страница 41: ...3 23 3 24 4 VIDEO OUTPUT CONNECTOR PART 1 2 3 BMK800 BMK800 BMK800 33PF 33PF 33PF...
Страница 42: ...3 25 3 26 5 AUDIO PART 1 3 4 2 Q712 KRA102S R774 R775 22 Q713 DGND 3 K7 CA_SPDIF_MUTE STI4600_RESET...
Страница 43: ...3 27 3 28 6 PVR CLOCK PART 1 2 3...
Страница 44: ...3 29 3 30 7 VSB VSB DECODER PART 1...
Страница 45: ...3 31 3 32 8 VSB DOWN CONVERTER PART 1...
Страница 46: ...3 33 3 34 9 MICOM DOWN CONVERTER PART 1...
Страница 47: ......
Страница 57: ...3 58 3 59 2 SYSTEM CIRCUIT DIAGRAM 1 SMEM_DATA S_MEM ADR PER_DATA PER_ADDR CPU CLOCK PCI BUS 03 3 15 HDR230...
Страница 59: ...3 62 3 63 4 SYSTEM CIRCUIT DIAGRAM 3 PER ADDR CLOCK P3 S MEM DATA S MEM ADDR PER DATA 03 3 15 HDR230...
Страница 60: ...3 64 3 65 5 VIDEO CIRCUIT DIAGRAM 1 PES CLOCK PER ADDR PER DATA Valid TP DATA CLK 03 3 15 HDR230 27...
Страница 61: ...6 VIDEO CIRCUIT DIAGRAM 2 PER ADDR VSB PDR TP DATA CLK VALID TP DATA CLK VALID 03 3 15 HDR230 3 66 3 67...
Страница 65: ...3 74 3 75 10 VSB CIRCUIT DIAGRAM IF VSB TP Data clock error valid 03 3 15 HDR230 DNS...
Страница 67: ...3 78 3 79 12 POWER IF COM VIDEO CIRCUIT DIAGRAM CVBS OUT Y OUT C OUT 03 3 15 HDR230...
Страница 68: ...3 80 3 81 13 FRONT CIRCUIT DIAGRAM RIGHT LEFT 03 3 15 HDR230...
Страница 69: ...3 82 3 83 8 PRINTED CIRCUIT DIAGRAMS 1 DIGITAL MAIN PRINTED CIRCUIT DIAGRAMS TOP...
Страница 70: ...3 84 3 85 2 DIGITAL MAIN PRINTED CIRCUIT DIAGRAMS BOTTOM...
Страница 71: ...3 86 3 87 3 KEY LEFT PRINTED CIRCUIT DIAGRAM 4 KEY RIGHT PRINTED CIRCUIT DIAGRAM LOCATION GUIDE...
Страница 72: ...3 88 3 89 5 POWER PRINTED CIRCUIT DIAGRAM LOCATION GUIDDE...