Yamaha YMF795 Скачать руководство пользователя страница 7

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YMF795

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Block Diagram

Concerning AIN signal inputted into equalizer circuit

It is possible to make the analog mixing between synthesizer output and other analog

source in the equalizer circuit and output the resulting sound through the speaker.

SYNC

SDIN

SCLK

CLK_I

/RST

/IRQ

EQ1

VREF

Serial

I/F

DVDD

FMVOL
32

-step

ower

down

Con

trol

Synthesizer

Simultaneous

sound generation

4-tone

DAC

AMP

AVDD

Timing Generator

OUT

HPVOL

-step

FIFO

16b

32w

EQ2

EQ3

VREF

CR circuit for E

SPVSS

SPVOL

-step

AIN

que

−

VREF

SPOUT1

SPOUT2

Содержание YMF795

Страница 1: ...drive the dynamic speaker with 500mW power allows connecting a speaker directly This LSI is equipped with an analog output pin also for the earphone jack In addition supporting the standby mode can re...

Страница 2: ...y Setting 24 On Interrupt Sequence 25 State Transition 26 Operation in FIFO empty condition 28 Reproduction method assuming occurrence of empty state 28 Example of peripheral circuit 29 1 Circuit diag...

Страница 3: ...register registers for start stop and tempo are provided In order to have sound generate the following controls must be performed to this LSI 1 Initial status setting cancellation of power down clock...

Страница 4: ...equentially starts reading the musical score data which have been stored in FIFO The processed musical score data are deleted 4 Timbre register block The block stores timbre data in this register whic...

Страница 5: ...figuration 24 pin SSOP TOP VIEW 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CLK_I NC SDIN SYNC SCLK NC AVSS VREF HPOUT EQ1 EQ2 EQ3 TESTO RST TESTI IRQ DVDD DVSS SPOUT2 SPOUT1 SPVSS...

Страница 6: ...arphone 10 EQ1 AO Equalizer pin 1 11 EQ2 AI Equalizer pin 2 12 EQ3 AO Equalizer pin 3 13 14 AVDD Analog power supply 3 3V Connect 0 1 F and 4 7 F capacitors between this pin and analog ground pin 15 1...

Страница 7: ...equalizer circuit and output the resulting sound through the speaker SYNC SDIN SCLK CLK_I RST IRQ EQ1 VREF Serial I F DVDD DVSS FMVOL 32 step Power down Control Register FM Synthesizer Simultaneous s...

Страница 8: ...T4 T3 T2 T1 T0 Tempo data 32h 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CLR ST FM Control 33h 0 0 0 0 0 0 0 0 0 0 0 0 0 CLKSEL CLK_I select 34h 0 0 0 0 0 0 0 0 0 0 IRQE IRQ Point IRQ Control 35h 0 0 0 0 0 0 0 0 0...

Страница 9: ...below can be generated Multiple 1 x1 Multiple 2 x2 Multiple 4 x4 BL 1 0 01b C 3 139Hz D3 147Hz D 3 156Hz E3 165Hz F3 175Hz F 3 185Hz G3 196Hz G 3 208Hz A3 220Hz A 3 233Hz B3 247Hz C4 262Hz C 4 277Hz D...

Страница 10: ...ough LSI never hangs unusual sound may be generated Never set it CH1 CH0 Part setting As the sound source section can simultaneously generate sounds in 4 parts set the part of a note by using CH1 and...

Страница 11: ...7h 12 8h 18 9h 24 Ah 48 Bh 0 Ch 16 Dh 24 Eh 36 Fh 48 TK2 TK0 Note sound length designation These 3 bits are used to designate the note sound length Depending on the value of interval setting TI3 0 th...

Страница 12: ...release time differs between carrier and modulator is present If operation is in the state completely stopped it shifts to the Attack rate in conjunction with KEY ON If the previous sound generation...

Страница 13: ...m number of timbres that can be simultaneously used is four the timbre can be changed during sound reproduction by setting these bits Set VCHE to 1 and set a timbre number by using VCH2 to VCH0 Switch...

Страница 14: ...ulator Index 2Eh 2Fh 8th timbre_ timbre data for the carrier The following bit assignment is used for both modulator and carrier The setting must be completed before any sound is generated Change of t...

Страница 15: ...hown as the time taken from 48dB to 0dB DR3 DR0 Decay Rate setting Decay Rate is a time interval taken for decay from 0 dB to the time it reaches at the Sustain Level SL The table on the next page is...

Страница 16: ...This function is used to set the envelope level TL TL5 TL4 TL3 TL2 TL1 TL0 Weighted bit dB 24 12 6 3 1 5 0 75 SUS Sustain On OFF setting 0 OFF 1 ON The Release Rate changes to 6 2 29s when the sound l...

Страница 17: ...23h is used 5h Timbre set in the Index of 24 to 27h is used 6h Timbre set in the Index of 28 to 2Bh is used 7h Timbre set in the Index of 2C to 2Fh is used 31h Tempo data This register sets tempo for...

Страница 18: ...CLKSEL 2 0 to 0h 34h Interrupt control Default 0000h Index b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 34h 0 0 0 0 0 0 0 0 0 0 IRQE IRQ point The musical score data is taken into the FIFO wh...

Страница 19: ...26 0Dh 18 15h 10 1Dh 2 06h 25 0Eh 17 16h 9 1Eh 1 07h 24 0Fh 16 17h 8 1Fh 0 38h Power Management control Default 001Eh Index b15 b14 b13 b12 b11 B10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 38h 0 0 0 0 0 0 0 0 0...

Страница 20: ...ck frequency MHz 000000000b Preset mode 000000001b Prohibition 000101111b Prohibition 000110000b 2 684658000 000110001b 2 740588375 111110001b 27 797396375 111110010b 27 853326750 111110011b Prohibiti...

Страница 21: ...AP1 is set to 1 the whole analog section stops Because an analog center voltage is made by VREF circuit AP2 This is the bit to power off the FM volume section EQ circuit speaker volume and non invert...

Страница 22: ...allocation 31h Tempo data 34h IRQ Control Cautions for cancellation of the power down 1 The time of 64 CLK_I is necessary from the setting of DP 0 until the digital section returns to the normal oper...

Страница 23: ...combined as shown below AP1 AP2 AP3 AP4 Caution Analog section whole power down 1 1 1 1 Be sure to set all volumes to MUTE first then set all bits to 1 simultaneously Use of only earphone output 0 1 1...

Страница 24: ...data 30h tempo data 31h and volumes 35 37h as required 4 Write musical score data 00h for 32 data that is to FIFO_FULL 5 Set the IRQ point value of 34h 6 Set the IRQE of 34h to 1 7 Set the ST bit of 3...

Страница 25: ...set IRQE to 0 and write the musical score data into the FIFO before it becomes empty As overwriting the data into the filled FIFO is prohibited write the data into FIFO by the amount not causing the...

Страница 26: ...urning the digital side power on to initialize the hardware is ideal If the analog power supply is turned on before the hardware is initialized noise may be generated Initialized Hardware Reset STOP P...

Страница 27: ...e of the analog and the digital section And shift to the power down mode from this state STOP This is a state in which volume mute cancellation and the timbre data setting has been completed In this s...

Страница 28: ...ds 33 words make the processing by the usual reproduction flow using interrupt 1 Complete the following procedure in advance Power ON Analog Power Down mode Initialized STOP See the figure of State Tr...

Страница 29: ...n this device therefore please design a board in consideration of noise to the RST line SCLK SDIN SYNC DVSS DVDD YMF795 RST 3 3V RESET SYNC SDIN SCLK CLK_I CLK AVDD AVSS IRQ IRQ SPOUT1 SPOUT2 VREF 0 1...

Страница 30: ...power supplies cannot be prepared please refer to 2 Circuit diagram and wiring diagram when one power supply and one voltage regulator IC are used And when 1 Circuit diagram and wiring diagram when t...

Страница 31: ...o AVSS pin near the LSI Excessive inductance between VSS pin and AVSS pin may cause malfunctions and failures Connect the ground pin of the voltage regulator IC used for analog circuits near AVSS pin...

Страница 32: ...e assumption that the device itself DC cut capacitor and a latter stage device will be in a normal operation Therefore it is also necessary to implement measures based on the assumption of these part...

Страница 33: ...that volume adjustment Total Level of Carrier of one tone is 0 dB An assumption of 300 mW output Output power of 300 mW can be obtained from the speaker when RL is 8 and a voltage between SPOUT1 and...

Страница 34: ...olume as 0dB EQ1 is 0 4125 Vp p and if Gain of the EQ amplifier is four times EQ3 becomes 1 65 Vp p When 4 dB is given by SPVOL voltage between SPOUT1 and 2 becomes 3 96 Vp p and resultantly 245 mW ou...

Страница 35: ...ded values R1 22 k and R2 82 k Gain 3 7 times Filter cutoff frequency of f1 and f2 is f1 1 2 R1 C1 f2 1 2 R2 C2 If C1 0 022 F and C2 120 pF the cutoff frequency of f1 330 Hz and f2 16 kHz Moreover the...

Страница 36: ...r R3 can obtain the following frequency characteristic Gain1 R2 R3 R1 Gain2 R3 R1 Filter cutoff frequency of f1 and f2 is f1 1 2 R1 C1 f2 1 2 R2 C2 f1 f2 Gain1 Gain1 3dB Gain Freq VREF EQ2 EQ3 FM VOL...

Страница 37: ...ention so that FIFO does not become empty when writing the musical score data into the FIFO About SYNC Both Type1 and Type2 in the above figure are available The LSI considers the rising edge of SYNC...

Страница 38: ...Symbol Min Typ Max Unit Operating voltage analog AVDD 3 0 3 3 3 6 V Operating voltage digital DVDD 3 0 3 3 3 6 V Operating ambient temperature TOP 40 25 85 C Note DVSS AVSS SPVSS 0V 3 DC characteristi...

Страница 39: ...Max Unit CLK_I clock period Tcclk_period 35 8 ns CLK_I L pulse width Tcclk_low 12 ns CLK_I H pulse width Tcclk_high 12 ns RST active L pulse width Trst_low 100 CLK_I SCLK start delay time after RST in...

Страница 40: ...ll time Tfall_sclk 20 ns SYNC H pulse width Tsync_high 100 ns SYNC rise time Trise_sync 20 ns SYNC fall time Tfall_sync 20 ns SYNC delay time Tdelay_SYNC 0 ns SYNC L pulse width SYNC_low 100 ns SYNC S...

Страница 41: ...8 Maximum output voltage amplitude RL 8 5 5 Vp p Maximum output power RL 8 THD N 1 0 500 mW THD N RL 8 f 1kHz 300mW output 0 025 Noise level without signal A filter 90 dBV Note TOP 25 C DVDD AVDD 3 3V...

Страница 42: ...load resistance 20 k Maximum output voltage amplitude 3 0 Vp p Output impedance 300 600 Note TOP 25 C DVDD AVDD 3 3V VREF Parameter Min Typ Max Unit VREF voltage 0 5 AVDD V Note TOP 25 C DVDD AVDD 3 3...

Страница 43: ...perators is called algorithm The operator in the front stage is called modulator and that in the rear stage carrier Each operator is capable of setting the frequency and the envelope waveform The conf...

Страница 44: ...YMF795 44 External dimensions...

Страница 45: ...YMF795...

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