Yamaha RX RX-Z7, Руководство по обслуживанию

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100
RX-Z7/DSP-Z7
RX-Z7/DSP-Z7
Pin No. Port Name Function Name (P.C.B.) I/O Detail of Function
M25 nRESET VNP2_N_RST MCU System reset terminal
T25 XI_S MCU System clock crystal oscillation terminal
T24 XO_S MCU System clock crystal oscillation terminal
AE24 XI_A MCU Audio clock crystal oscillation terminal
AD24 XO_A MCU Audio clock crystal oscillation terminal
T22 TEST0 TEST0 MCU System reset terminal
R23 TEST1 MCU Test mode setting
T23 TEST2 MCU Test mode setting
AA3 nTRST VNP2_N_TRST MCU
AB1 TDI VNP2_TDI MCU
AC1 TDO VNP2_TDO MCU
AA2 TCK VNP2_TCK MCU
AB3 TMS TNP2_TMS MCU
AB2 RTCK MCU
L23 nSCS3 CS Chip select 3 for accessing YGV619 MEM
L24 nSCS2 CS Chip select 2 for accessing YGV619 REG
K23 nSCS1 CS Chip select 1 for accessing Flash ROM
K24 nSCS0 CS Chip select 0 for accessing NPGA
J23 nSLBE BUS Lower byte write enable
J24 nSUBE BUS Upper byte write enable
K25 nSWR BUS 8bit device write enable
J25 nSRD BUS Read enable
** SA[22:0] BUS
SRAM address bus / CS0 space
CS1 space
CS2 space
CS3 space
** SD[15:0] BUS SRAM data bus
B1 SCLK0 BUS SDRAM clock
C1 SCKE0 BUS SDRAM clock enable
D1 SCLK1 BUS SDRAM clock
E1 SCKE1 BUS SDRAM clock enable
F1 nCS1 CS SDRAM chip select 1
C2 nCS0 CS SDRAM chip select 0
E3 nWE BUS SDRAM write enable
F2 nRAS BUS SDRAM row address strobe
E2 nCAS BUS SDRAM column address strobe
A9 DQM3 BUS SDRAM data input/output mask 3
B9 DQM2 BUS SDRAM data input/output mask 2
C9 DQM1 BUS SDRAM data input/output mask 1
C10 DQM0 BUS SDRAM data input/output mask 0
** A[11:0] BUS SDRAM address bus
F3 A12 BUS
J2 A13 BUS
J1 A14 BUS
** D[31:0] BUS SDRAM data bus
L25 nINT0 VNP2_TCK IRQ
M24 nINT1 M2V_N_INT_3 IRQ Interrupt input from main microprocessor
M23 nINT2 GA_N_INT IRQ Interrupt input from NPGA
AE7 TXD0/AGPIO[3] DBG_TXD SO For debugging
AE8 RXD0/AGPIO[0] DBG_RXD SI For debugging
AD7 nCTS0/AGPIO[4] DBG_LED0 O LED output 0 for debugging
AD8 nRTS0/AGPIO[1] DBG_LED1 O LED output 1 for debugging
AC8 EXTCLK0/AGPIO[2] V2M_N_INT_3 O Interrupt output from main microprocessor
AE5 TXD1/AGPIO[9] VCPU_TXD_3 SO
Communication between microprocessors
(Asynchronous)
AE6 RXD1/AGPIO[6] VCPU_RXD SI
Communication between microprocessors
(Asynchronous)
AD5 nCTS1/AGPIO[10] VCPU_N_CTS SI
Communication between microprocessors
(Asynchronous)
AD6 nRTS1/AGPIO[7] VCPU_N_RTS_3 SO
Communication between microprocessors
(Asynchronous)
AC6 nDCD1/AGPIO[8] DEV_N_RST O System reset