PC6501N/PC4801N/PC3301N/PC2001N
16
■
LSI PIN DESCRIPTION
(LSI 端子機能表)
• HD64F7044F28V
(X5719B00)
CPU
PIN
NO.
NAME
I/O
FUNCTION
PIN
NO.
NAME
I/O
FUNCTION
1 PE1/TIOC4C/DACK0/AH
_____
I/O
Port E / MTU I/O / DMA transfer strobe / Address hold
57
PD11/D11
I/O
Port D / Data bus
2 PE15/TIOC4D/DACK1/IRQOUT I/O
Port E / MTU I/O / DMA transfer strobe / Interrupt request output
58
PD10/D10
I/O
3
Vss
I
Ground
59
PD9/D9
I/O
4
PC0/A0
O
Port C / Address bus
60
PD8/D8
I/O
5
PC1/A1
O
61
Vss
I
Ground
6
PC2/A2
O
62
PD7/D7
I/O
Port D / Data bus
7
PC3/A3
O
63
PD6/D6
I/O
8
PC4/A4
O
64
PD5/D5
I/O
9
PC5/A5
O
65
Vcc
I
Power supply
10
PC6/A6
O
66
PD4/D4
I/O
Port D / Data bus
11
PC7/A7
O
67
PD3/D3
I/O
12
PC8/A8
O
68
PD2/D2
I/O
13
PC9/A9
O
69
PD1/D1
I/O
14
PC10/A10
O
70
PD0/D0
I/O
15
PC11/A11
O
71
Vss
I
Ground
16
PC12/A12
O
72
XTAL
I
Crystal oscillator
17
PC13/A13
O
73
MD3
I
Mode set
18
PC14/A14
O
74
EXTAL
I
External clock
19
PC15/A15
O
75
MD2
I
Mode set
20
PB0/A16
O
Port B / Address bus
76
NMI
I
Non-maskable interrupt request
21
Vcc
I
Power supply
77
Vcc
I
Power supply
22
PB1/A17
O
Port B / Address bus
78
MD1
I
Mode set
23
Vss
I
Ground
79
MD0
I
24 PB2/IRQ0
________
/POE0
_________
/RAS
_______
I/O
Port B / Interrupt request / Port output enable / Row address strobe
80
PLLVcc
I
PLL power supply
25 PB3/IRQ1
________
/POE1
________
/CASL
________
I/O
Port B / Interrupt request / Port output enable / Lower column address strobe
81
PLLCAP
I
PLL capacitance
26 PB4/IRQ2
________
/POE2
________
/CASH
________
I/O
Port B / Interrupt request / Port output enable / Upper column address strobe
82
PLLVss
I
PLL ground
27
Vss
I
Ground
83
PA15/CK
O
Port A / System clock
28 PB5/IRQ3
________
/POE3
_________
/RDWR I/O
Port B / Interrupt request / Port output enable / DRAM read/write
84
RES
_______
I
Power-on reset
29 PB6/IRQ4
_________
/A18/ BACK
___________
I/O
Port B / Interrupt request / Address bus / Bus request acknowledge
85 PE0/TIOC0A/DREQ0
____________
I/O
Port E / MTU I/O / DMA transfer request
30 PB7/IRQ5
_________
/A19/BREQ
___________
I/O
Port B / Interrupt request / Address bus / Bus request
86 PE1/TIOC0B/DRAK0 I/O
Port E / MTU I/O / DREQ request acknowledgement
31 PB8/IRQ6
_________
/A20/ WAIT
__________
I/O
Port B / Interrupt request / Address bus / Wait
87 PE2/TIOC0C/DREQ1
____________
I/O
Port E / MTU I/O / DMA transfer request
32 PB9/IRQ7
_________
/A21/ADTRG
____________
I/O
Port B / Interrupt request / Address bus / A/D conversion trigger input
88 PE3/TIOC0D/DRAK1 I/O
Port E / MTU I/O / DREQ request acknowledgement
33
Vss
I
Ground
89
PE4/TIOC1A
I/O
Port E / MTU I/O
34
PA14/RD
_____
O
Port A / Read
90
Vss
I
Ground
35
WDTOVF
_______________
O
Watchdog time overflow
91
PF0/AN0
I
Port F / Analog input
36
PA13/WRH
________
O
Port A / Upper write
92
PF1/AN1
I
37
Vcc
I
Power supply
93
PF2/AN2
I
38
PA12/WRL
________
O
Port A / Lower write
94
PF3/AN3
I
39
Vss
I
Ground
95
PF4/AN4
I
40
PA11/CS1
_______
O
96
PF5/AN5
I
97
AVss
I
Analog ground
Port A / MTU timer clock input / Interrupt request
98
PF6/AN6
I
Port F / Analog input
99
PF7/AN7
I
Port A / MTU timer clock input / Chip select
100
AVcc
I
Analog power supply
101
Vss
I
Ground
Port A / Serial clock / DMA transfer request / Interrupt request 102
PE5/TIOC1B
I/O
Port E / MTU I/O
Port A / Data transmission
103
Vcc
I
Power supply
104
PE6/TIOC2A
I/O
Port E / MTU I/O
Port A / Serial clock / DMA transfer request / Interrupt request 105
PE7/TIOC2B
I/O
Port A / Data transmission
106
PE8/TIOC3A
I/O
107
PE9/TIOC3B
I/O
108
PE10/TIOC3C
I/O
109
Vss
I
Ground
54
PD13/D13
I/O
110
PE11/TIOC3D
I/O
Port E / MTU I/O
55
Vss
I
Ground
111
PE12/TIOC4A
I/O
56
PD12/D12
I/O
Port D / Data bus
112 PE13/TIOC4B/MRES
__________
I/O
Port E / MTU I/O / Manual reset
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