Pin No.
Port Name
Function Name
Condition When Used
Detail of Function
I/O
Logic
W2
SPI_SDO
VNP2_FL_MOSI
O
Data
IF data output (FLD CPU
↔
Main microprocessor)
For FL microprocessor control
N25
BGPIO[16]
VNP2_FL_LAT
O
IF data update decision edge output
(FLD CPU
↔
Main microprocessor)
For FL microprocessor control
N24
BGPIO[17]
VNP2_FL_CTL
O
IF status (VFD1/VFD2
↔
Main microprocessor)
0: Lights / 1: Lights off
For FL microprocessor control
N23
BGPIO[18]
FLD_ACK(FLD_WAIT_
REQ)
I
IF transfer permission
(VFD1/VFD2
↔
Main microprocessor)
For FL microprocessor control
P25
BGPIO[19]
VNP2_FL_CS
O
–
IF chip select (VFD1/VFD2
↔
Main microprocessor)
P24
BGPIO[20]
BGPIO20
–
–
Empty
P23
BGPIO[21]
REV0
I
Data
H: 2 types of crystals used / L: 1 type of crystal used
Y2
BGPIO[2]
DAC_SCK
–
Clock
DAC clock out
For PCM1792A control
R25
BGPIO[22]
(RY_UNBAL)
O
H act
UNBALANCE (XLR) output relay control
H: Relay on / L: Relay
R24
BGPIO[23]
(RY_BAL)
O
H act
BALANCE (RCA) output relay control
H: Relay on / L: Relay off
R1
SDO_ABCK
NCPU_BCK
O
Clock
Audio output bit clock
U2
BGPIO[11]
DAC_CSR
O
–
DACR ch chip select
For PCM1792A control
P1
SDO_AWCK
NCPU_WCK
O
Clock
Audio output word clock
U3
BGPIO[12]
DAC_N_IC
O
–
DAC initial clear
For PCM1792A control
U1
SDO_MCK
NCPU_MCK
O
Clock
Audio output master clock
P2
SDO3
O
Data
No used (For multi channel)
P3
SDO2
O
Data
No used (For multi channel)
R2
SDO1
O
Data
No used (For multi channel)
R3
SDO0
NCPU_SD0
O
Data
Audio output data 0
N1
SDI_ABCK
I
Clock
No used
T2
BGPIO[14]
DBG_DIP0
I
Data
DIP SW0 for debugging
M1
SDI_AWCK
I
Clock
No used
T3
BGPIO[15]
DBG_DIP1
I
Data
DIP SW0 for debugging
T1
SDI_MCK
22M
I
Clock
Audio clock crystal oscillator
M2
SDI3
I
Data
No used
M3
SDI2
I
Data
No used
N2
SDI1
I
Data
No used
N3
SDI0
I
Data
No used
Pin No.
Port Name
Function Name
Condition When Used
Detail of Function
I/O
Logic
AE16
USBP
USBP
B
Data
USB data +
AD16
USBM
USBM
B
Data
USB data -
AB16
USB_PWEN
USB_PWEN
O
H act
USB power enable
AC17
USB_OC
USB_OC
I
H act
USB over current detection
AE12
MAC_REF_CLK
PHY01_REF_CLK
O
Clock
MAC0 RMII clock output
AE13
MAC0_RXD1
PHY0_RXD1
I
Data
MAC0 RMII reception data 1
AD13
MAC0_RXD0
PHY0_RXD0
I
Data
MAC0 RMII reception data 0
AC13
MAC0_RXER
PHY0_RXER
I
Data
MAC0 RMII reception error
AE14
MAC0_TXD1
PHY0_TXD1
O
Data
MAC0 RMII transmission data 1
AD14
MAC0_TXD0
PHY0_TXD0
O
Data
MAC0 RMII transmission data 0
AC14
MAC0_TXEN
PHY0_TXEN
O
Data
MAC0 RMII transmission enable
AD12
MAC0_CRS_DV
PHY0_CRS_DV
I
Data
MAC0 RMII career detection
AE15
MAC0_MDC
PHY0_MDC
O
Clock
MAC0 RMII MI clock
AD15
MAC0_MDIO
PHY0_MDIO
B
Data
MAC0 RMII MI data
AE10
MAC1_RXD0
I
Data
No used (MAC1 RMII reception data 0)
AD10
MAC1_RXD1
I
Data
No used (MAC1 RMII reception data 1)
AC10
MAC1_RXER
I
Data
No used (MAC1 RMII reception error)
AE11
MAC1_TXD0
O
Data
No used (MAC1 RMII transmission data 0)
AD11
MAC1_TXD1
O
Data
No used (MAC1 RMII transmission data 1)
AC11
MAC1_TXEN
O
Data
No used (MAC1 RMII transmission enable)
AC12
MAC1_CRS_DV
I
Data
No used (MAC1 RMII career detection)
AE9
MAC1_MDC
O
Clock
No used (MAC1 RMII MI clock)
AD9
MAC1_MDIO
B
Data
No used (MAC1 RMII MI data)
NP-S2000
47
