MG12/4FX
20
IC BLOCK DIAGRAM
（IC ブロック図）
(X5219A00)
AK5381VT-E2
A/D Converter
PCM1742KEG/2K (X3538A00)
Digital to Analog Converter
1
2
3
4
5
6
7
16
15
14
13
12
11
SCK
ML
MC
MD
ZEROL/NA
ZEROR/ZEROA
V
COM
8
9
10
AGND
BCK
DATA
LRCK
DGND
V
DD
V
CC
V
OUT
L
V
OUT
R
Pin No. Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O
I
I
I
-
-
-
O
O
-
-
O
O
I
I
I
I
BCK
DATA
LRCK
DGND
V
DD
V
CC
V
OUT
L
V
OUT
R
AGND
V
COM
ZEROR/ZEROA
ZEROL/NA
MD
MC
ML
SCK
Function
Audio Data Bit Clock Input
(1)
Audio Data Digital Input
(1)
L-Channel and R-Channel Audio Data Latch Enable Input
(1)
Digital Ground
Digital Power Supply, +3.3V
Analog Power Supply, +5V
Analog Output for L-Channel
Analog Output for R-Channel
Analog Ground
Common Voltage Decoupling
Zero Flag Output for R-Channel/Zero Flag Output for L/R-Channel
Zero Flag Output for L-Channel/No Assign
Mode Control Data Input
(2)
Mode Control Clock Input
(2)
Mode Control Latch Input
(2)
System Clock Input
Notes: (1) Schmitt-trigger input, 5V tolerant. (2) Schmitt-trigger with internal pull-down, 5V tolerant.
Audio
Serial
Port
Output Amp and
Low-Pass Filter
DAC
4x/8x
Oversampling
Digital Filter
with
Function
Controller
Enhanced
Multilevel
Delta-Sigma
Modulator
Output Amp and
Low-Pass Filter
DAC
BCK
LRCK
DATA
ML
MC
MD
Serial
Control
Port
Power Supply
V
OUT
L
V
COM
V
OUT
R
V
DD
DGND
ZEROR
System Clock
V
CC
AGND
5
1
2
3
4
6
7
8
9
10
13
14
15
1
2
3
4
5
6
7
16
15
14
13
12
11
CKS0
CKS2
DIF
PDN
SCLK
MCLK
LRCK
8
9
10
SDTO
AINR
AINL
CKS1
VCOM
AGND
VA
VD
DGND
Pin No. Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
I/O
I
I
I
O
-
-
-
-
O
I/O
I
I/O
I
I
I
I
AINR
AINL
CKS1
VCOM
AGND
VA
VD
DGND
SDTO
LRCK
MCLK
SCLK
PDN
DIF
CKS2
CKS0
Function
Rch Analog Input Pin
Lch Analog input Pin
Mode Select 1 Pin
Common Voltage Output Pin, VA/2
Bias voltage of ADC input.
Analog Ground Pin
Analog Power Supply Pin, 4.5 ~ 5.5V
Digital Power Supply Pin,
2.7 ~ 5.5V(Fs=4K ~ 48kHz), 3.0 ~ 5.5V(Fs=48k ~ 96kHz)
Digital Ground Pin
Audio Serial Data Output Pin
"L" Output at Power-down mode.
Output Channel Clock Pin
"L" Output in Master Mode at Power-down mode.
Master Clock Input Pin
Audio Serial Data Clock Pin
"L" Output in Master Mode at Power-down mode.
Power Down mode Pin
"H":Power up, "L":Power down
Audio Interface Format Pin
"H":24bit I
2
S Compatible, "L":24bit MSB justified
Mode Select 2 Pin
Mode Select 0 Pin
Note: All input pins should not be left floating.
2
11
1
3
16
10
13
12
9
7
8
4
15
6
5
14
AINL
CKS2
MCLK
VA AGND VD DGND
CKS1
LRCK
CKS0
SCLK
SDTO
AINR
VCOM
DIF
PDN
Voltage
Reference
Clock
Divider
Serial I/O
Interface
Decimation
Filter
Decimation
Filter
Modulator
Modulator
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QQ 376315150
9
9
2
8
9
4
2
9
8
TEL 13942296513
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
