Yamaha HTR-6290, Руководство по обслуживанию

Страница: 82 / 198

RX-V1900/HTR-6290/DSP-AX1900
82
RX-V1
90
0/HTR-6290/
DSP-AX1
90
0
No. Function Name TYPE
(1)
PULL
(2)
GPIO
(3)
Detail of Function
1 Ground(Vss)
2 AHCLKX0/AHCLKX2 IO – Y McASP0 and McASP2 transmit master clock
3 AMUTE0 IO – Y McASP0 mute output
4 AMUTE1 IO – Y McASP1 mute output
5 AHCLKX1 IO – Y McASP1 transmit master clock
6 Ground(Vss)
7 ACLKX1 IO – Y McASP1 transmit bit clock
8 Core Supply (CVpp)
9 ACLKR1 IO – Y McASP1 receive bit clock
10 IO Supply (DVpp)
11 AFSX1 IO – Y McASP1 transmit frame Sync (L/R clock)
12 AFSR1 IO – Y McASP1 receive frame Sync (L/R clock)
13 Ground(Vss)
14 RESET IO – N Device reset pin
15 Ground(Vss)
16 Core Supply (CVpp)
17 CLKIN IO – N Alternate clock input (3.3-V LVCMOS input)
18 Ground(Vss)
19 TMS IO IPU N Test mode select
20 Core Supply (CVpp)
21 TRST IO IPU N Test reset
22 OSCVss PWR – N Oscillator Vss tap point (for filter only)
23 OSCIN IO – N 1.2-V oscillator input
24 OSCOUT O – N 1.2-V oscillator output
25 OSCVpp PWR – N Oscillator 1.2-V Vpp tap point (for filter only)
26 Ground(Vss)
27 PLLHV PWR – N PLL 3.3-V supply input (requires external filter)
28 TDI IO IPU N Test data in
29 TDO OZ IPU N Test data out
30 Ground(Vss)
31 IO Supply (DVpp)
32 EMU[0] IO IPU N Emulation pin 0
33 Core Supply (CVpp)
34 EMU[1] IO IPU N Emulation pin 1
35 TCK IO IPU N Test clock
36 Ground(Vss)
37 EM_CAS O – N SDRAM column address strobe
38 EM_WE O – N SDRAM write enable
39 EM_WE_DQM[0] O – N Write enable or byte enable for EM_D [7:0]
40 Ground(Vss)
41 EM_D[7] IO – N EMIF data bus [lower 16-bits]
42 IO Supply (DVpp)
43 EM_D[6] IO – N EMIF data bus [lower 16-bits]
44 Core Supply (CVpp)
45 EM_D[5] IO – N EMIF data bus [lower 16-bits]
46 EM_D[4] IO – N EMIF data bus [lower 16-bits]
47 Ground(Vss)
48 EM_D[3] IO – N EMIF data bus [lower 16-bits]
49 EM_D[2] IO – N EMIF data bus [lower 16-bits]
50 IO Supply (DVpp)
51 EM_D[1] IO – N EMIF data bus [lower 16-bits]
52 EM_D[0] IO – N EMIF data bus [lower 16-bits]
53 Core Supply (CVpp)
54 Ground(Vss)
55 EM_D[15] IO – N EMIF data bus [lower 16-bits]
56 EM_D[14] IO – N EMIF data bus [lower 16-Bits]
57 Core Supply (CVpp)
58 EM_D[13] IO – N EMIF data bus [lower 16-Bits]
59 EM_D[12] IO – N EMIF data bus [lower 16-Bits]
60 IO Supply (DVpp)
61 EM_D[11] IO – N EMIF data bus [lower 16-Bits]
62 Ground(Vss)
63 EM_D[10] IO – N EMIF data bus [lower 16-Bits]