Yamaha HTR-6050, Руководство по обслуживанию

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RX-V561/HTR-6050
RX-V561/HTR-6050
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40
INT1
BOUT
TVDD
DVDD
DVSS
XTO
XTI
TEST3
MCKO2
MCKO1
COUT
UOUT
VOUT
SDTO2
BICK2
LRCK2
SDTO1
BICK1
LRCK1
CDTO
CCLK
SCL
CDTI
SDA
CSN
DAUX1
SDTI4
SDTI3
SDTI2
SDTI1
XTL1
XTL0
PDN
MASTER
DZF2
OVF
DZF1
LOUT4
NC
ROUT4
NC
LOUT3
NC
O
O
–
–
–
O
I
I
O
O
O
O
O
O
I/O
I/O
O
I/O
I/O
O
I
I
I
I/O
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
–
O
–
O
–
Interrupt 1 pin
Block-start output pin for receiver input “H” during first 40 flames
Output buffer power supply pin, 2.7 V to 5.5 V
Digital power supply pin, 4.5 V to 5.5 V
Digital ground pin
X’tal clock output pin
X’tal / External clock input pin
Test 3 pin
This pin should be connected to DVSS
Master clock output 2 pin
Master clock output 1 pin
C-bit output pin for receiver input
U-bit output pin for receiver input
V-bit output pin for receiver input
Audio serial data output pin (DIR/DIT part)
Audio serial data clock pin (DIR/DIT part)
Channel clock pin (DIR/DIT part)
Audio serial data output pin (ADC/DAC part)
Audio serial data clock pin (ADC/DAC part)
Input channel clock pin
Control data output pin in serial mode, I2C pin= “L”
Control data clock pin in serial mode, I2C pin= “L”
Control data clock pin in serial mode, I2C pin= “H”
Control data input pin in serial mode, I2C pin= “L”
Control data pin in serial mode, I2C pin= “H”
Chip select pin in serial mode, I2C pin=”L”
This pin should be connected to DVSS, I2C pin=”H”
AUX audio serial data input pin (ADC/DAC part)
DAC4 audio serial data input pin
DAC3 audio serial data input pin
DAC2 audio serial data input pin
DAC1 audio serial data input pin
X’tal frequency select 0 pin
X’tal frequency select 1 pin
Power-down mode pin
When “L”, the AK4588 is powered-down, all output pin goes “L”, all registers are reset
When CAD1-0 pins are changed, the AK4588 should be reset by PDN pin
Master mode select pin
“H”: Master mode, “L”: Slave mode
Zero input detect 2 pin (table 13)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data, this pin
goes to “H” / When RSTN1 bit is “0” or PWDAN bit is “0”, this pin goes to “H”
Analog input overflow detect pin
This pin goes to “H” if the analog input of L ch or R ch overflows
This pin becomes OVF pin if OVFE bit is set to 1
Zero input detect 1 pin (table 13)
When the input data of the group 1 follow total 8192 LRCK cycles with “0” input data, this pin
goes to “H” / When RSTN1 bit is “0” or PWDAN bit is “0”, this pin goes to “H”
DAC4 L ch analog output pin
No connect pin
No internal bonding / This pin should be opened
DAC4 R ch analog output pin
No connect pin
No internal bonding / This pin should be opened
DAC3 L ch analog output pin
No connect pin
No internal bonding / This pin should be opened
Pin No. Function Name I/O Detail of Function