Yamaha GX-500, Руководство по обслуживанию

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GX-500/GX-500VCD
GX-500/VCD
58
X1
59
X2
79
MSEL
77
CSEL
20
PMCK
63
FCLK
19
SMCK
61
BYTCK
49
VCOF
52
CK384(EFM)
TIMING
GENERATOR
PITCH CONTROL
VCO
MICRO COMPUTER
INTERFACE
OUTPUT
PORT
29
VREF
26
KICK
21
TR
V
8
M
D
ATA
7
MCLK
9
MLD
78
PSEL
76
RSEL
44
ARF
46
DRF
45
IREF
47
DSLF
48
PLLF
52
EFM
53
PCK
DSL ¥ PLL VCO
50
A
VDD2
51
A
VSS2
70
IOSEL
78
SRDA
T
AIN(PSEL)
79
LRCKIN(MSEL)
80
BCLKIN(SSEL)
15
SUBQ
14
SQCK
80
SSEL
69
FLAG6(RESY)
SUB CODE
BUFFER
69
RESY
68
DEMPH
55
SUBC
56
SBCK
62
CLDCK
13
BLKCK
67
CRC
66
CL
VS
EFM DEMODULATION
SYNC INTERPOLATION
SUB-CODE DEMODULATION
CIRC ERROR CORRECTION
DEINTERLEAVE
16K
SRAM
16
DMUTE
1
BCLK
3
SRDA
T
A
2
LRCK
10
SENSE
43
WVEL
40
LDON
42
PLA
Y
11 12 41
TES
30
FBAL
31
TBAL
28
FOD
27
TRD
22
TVD
25
ECS
54
T
OFS
61
TR
VSTP(BYTCK)
D/A
CONVERTER
/FLOCK /TLOCK
INTERPOLATION
SOFT MUTING
DIGITAL
ATTENUATION
PEAK DETECT
AUTO CUE
CLV
SERVO
DIGITAL
AUDIO
INTERFACE
23
PC
24
ECM
6
TX
64 65
FLAG
DIGITAL DEEMPHASIS
73
OUTL
75
OUTR
PWM
(L)
PWM
(R)
1-BIT DAC
8 TIMES
OVER SAMPLING
DIGITAL FILTER
72
A
VDD1
74
A
VSS1
SERVO
CPU
IPFLAG
VDD
VSS
DVDD1
/RST
/TEST
DVSS1
FE
TE
RFENV
TRCRS
VDET
BDO
/RFDET
OFT
17
S
TAT
60
57
4
5
18
71
32
33
34
37
35
39
38
36
A/D
CONVER
TER
INPUT
POR
T
SER
VO
TIMING GENERA
T
O
R
IC5 : MN662741RPB1 [P.C.B. CD/VCD]
Signal Processor & Controller
■
IC DATA
26
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Function
Bit clock output for SRDATA
L/R identification signal output H : L-ch audio data L : R-ch audio data
Serial data output
Power supply for digital circuits (+5)
GND for digital circuits
Digital audio interface output signal
Microcomputer command clock signal input (Latches the data at a rising edge)
Microcomputer command data input
Microcomputer command load signal input L : Load
Sense signal output (OFT, FESL, NACEND, NAJEND, SFG, NWTEND)
Focus servo pull-in signal (L : Pull-in status)
Tracking servo pull-in signal (L : Pull-in status)
Sub-code block clock signal (f
BLKCK
=75Hz)
External clock input for sub-code Q register
Sub-code Q data output
Muting input H : Mute
Status signal (CRC, CUE, CLVS, TTSTOP, FCLV, SQOK, FLAG6, SENSE, FLOCK, TLOCK)
Reset input (Reset when being at L for 472 ns or longer at IOSEL = L) L : Reset
8.4672MHz clock signal output at MSEL = H 4.2336MHz clock signal output at MSEL = L (NC)
88.2kHz clock signal output (NC)
Traverse (Feed) forced feed output 3-State
Traverse (Feed) drive output
Spindle motor ON signal L : ON (NC)
Spindle motor drive signal (Forced mode output) 3-State
Spindle motor drive signal (Servo error signal output)
Kick pulse output 3-State
Tracking drive output
Focus drive output
Name
BCLK
LRCK
SRDATA
DVDD1
DVSS1
TX
MCLK
MDATA
MLD
SENSE
FLOCK
TLOCK
BLKCK
SQCK
SUBQ
DMUTE
STAT
RST
SMCK
PMCK
TRV
TVD
PC
ECM
ECS
KICK
TRD
FOD
I/O
O
O
O
I
I
O
I
I
I
O
O
O
O
I
O
I
O
I
O
O
O
O
O
O
O
O
O
O