Yamaha DVD-S1700, Руководство по обслуживанию

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DVD-S1700
20
DVD-S1700
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
H_A[1]
H_DQ[15]
H_DQ[14]
GND_IO1
H_DQ[13]
H_DQ[12]
H_DQ[11]
H_DQ[10]
H_DQ[9]
VCC_IO1
H_DQ[8]
H_DQ[7]
H_DQ[6]
H_DQ[5]
H_DQ[4]
H_DQ[3]
GND_IO2
H_procclock
VCC_Core1
GND_Core1
sys_clk
H_DQ[2]
H_DQ[1]
H_CSn
H_DQ[0]
H_RWn
H_WAIT
H_IRQn
aud_clk
PCM_dclk_in
PCM_wclk_in
V
DDA
V
SSA
biasin
Agcinp
Adcrefl
V
CC
_IO7
GND_IO7
PCM_CeLf_in
PCM_LeRi_in
PCM_LsRs_in
B_FLAG/SERR
B_SYNC/Sync
B_WCLK/SENB
B_DATA/Be_dat(0)
B_BCLK/SDCLK
UDE_req
Data_req
Be_dat(1)
Be_dat(2)
Be_dat(3)
Be_dat(4)
Be_dat(5)
Be_dat(6)
Be_dat(7)
TRST
TMS
VCC_IO2
TDO
TDI
TCK
H_sel[0]
H_sel[1]
Address bus
Data bus
Data bus
GND I/O pads
Data bus
Data bus
Data bus
Data bus
Data bus
Vcc_I/O pads
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
GND I/O pads
Host processor EMI interface clock
Core supply voltage
Core ground
System clock
Data bus
Data bus
Host chip select; active LOW
Data bus
Read = 1; Write = 0
Wait signal
Interrupt request; active LOW
DSD audio clock
PCM data clock
PCM word clock
V
DD
of ADC
V
SS
of AGC and ADC;
Connected to substrate
Bias current input
AGC positive input signal; HF in
ADC decoupling
VCC I/O pads
GND I/O pads
PCM data center or LFE
PCM data left or right
PCM data left or right surround
I
2 S-bus flag (EDC flag)
Sector sync or absolute time sync
I
2
S-bus word clock or UDE data
sense from host
I
2
S-bus data or LSB data of parallel interface
I
2
S-bus bit clock
Host request data from front-end;
routed via the SAA7893HL
Data request for UDE
Front-end parallel data interface
Front-end parallel data interface
Front-end parallel data interface
Front-end parallel data interface
Front-end parallel data interface
Front-end parallel data interface
Front-end parallel data interface
Boundary scan reset
Boundary scan mode select
V
CC
I/O pads
Output
Boundary scan data input
Boundary scan clock
Host select signals: SAD16,
MAD16 and SAD08
Host select signals: SAD16,
MAD16 and SAD08
IN
I/O10
I/O10
GND_IO
I/O10
I/O10
I/O10
I/O10
I/O10
VCC_IO1
I/O10
I/O10
I/O10
I/O10
I/O10
I/O10
GND_IO
IN
VCC_core
GND_core
IN
I/O10
I/O10
IN
I/O10
IN
O10
O10
IN
IN
IN
VDDCO
VSSCO
APIO
APIO
APIO
VCC_IO
GND_IO
IN
IN
IN
IN
IN
IN
IN
IN
IN
O10
IN
IN
IN
IN
IN
IN
IN
IN1
IN1
VCC_IO
O10
IN1
IN
IN
IN
Pin
Symbol Description
Type[1]
Pin.
Symbol
Type
[1]
Description
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
D_ADDR[3]
D_ADDR[4]
D_ADDR[2]
D_ADDR[5]
D_ADDR[1]
GND_IO3
D_ADDR[6]
D_ADDR[0]
D_ADDR[7]
D_ADDR[10]
D_ADDR[8]
D_ADDR[13]
VCC_IO3
D_ADDR[9]
D_ADDR[12]
D_ADDR[11]
D_Wen
D_RASn
D_CASn
GND_IO4
GND_Core2
VCC_Core2
D_clk
D_DQ[5]
D_UDQM
D_LDQM
D_DQ[7]
D_DQ[8]
VCC_IO4
D_DQ[6]
D_DQ[9]
D_DQ[10]
D_DQ[4]
D_DQ[11]
D_DQ[3]
GND_IO5
D_DQ[12]
D_DQ[2]
D_DQ[13]
D_DQ[1]
D_DQ[14]
D_DQ[0]
VCC_IO5
D_DQ[15]
DSD_PCM_0
DSD_PCM_1
DSD_PCM_2
DSD_PCM_3
GND_IO6
DSD_PCM_4
DSD_PCM_5
DSD_PCM_6
DSD_PCM_7
DSD_PCM_8
VCC_IO6
DSD_PCM_10
DSD_PCM_9
DSD_PCM_11
RESETn
H_A_sel
H_A[6]
H_A[5]
H_A[4]
H_A[3]
H_A[2]
O10
O10
O10
O10
O10
GND_IO
O10
O10
O10
O10
O10
O10
VCC_IO
O10
O10
O10
O10
O10
O10
GND_IO
GND_core
VCC_core
O10
I/O10
O10
O10
I/O10
I/O10
VCC_IO
I/O10
I/O10
I/O10
I/O10
I/O10
I/O10
GND_IO
I/O10
I/O10
I/O10
I/O10
I/O10
I/O10
VCC_IO
I/O10
O10
O10
O10
O10
GND_IO
O10
O10
O10
O10
O10
VCC_IO
O10
O10
O10
IN
IN
IN
IN
IN
IN
IN
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
GND I/O pads
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
SDRAM address bus
Vcc I/O pads
SDRAM address bus
SDRAM address bus
SDRAM address bus
Read or write
Row address select; active LOW
Column address select; active LOW
GND I/O pads
Core ground
Core supply voltage
Clock signal needed for SDRAM
Data bus
DQ mask enable (upper)
DQ mask enable (lower)
Data bus
Data bus
Vcc I/O pads
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
GND I/O pads
Data bus
Data bus
Data bus
Data bus
Data bus
Data bus
Vcc_IO pads
Data bus
6-channel data output
6-channel data output
6-channel data output
6-channel data output
GND I/O pads
6-channel data output
6-channel data output
6-channel data output
6-channel data output
2-channel data output
V
CC
I/O pads
2-channel data output
2-channel clock or control
2-channel data output
Asynchronous reset; active LOW
Address select
Address bus
Address bus
Address bus
Address bus
Address bus