Yamaha D24, Руководство по обслуживанию

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D24
27
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
CKS
DVDD
DVSS
XTO
XTI
/PD
BICK
SDATA
LRCK
SMUTE
DFS
DEM0
I
-
-
O
I
I
I
I
I
I
I
I
Clock selection
Digital power supply
Digital ground
Clock output
Clock input
Power down reset
Serial bit clock
Serial data
L/R clock
Soft mute
Sampling mode selection
De-emphasis selection 13
14
15
16
17
18
19
20
21
22
23
24 DEM1
DIF0
DIF1
BVDD
AOUTR
AOUTL
VCOM
AVDD
AVSS
VREF
DZF
TTL
I
I
I
-
O
O
O
-
-
I
O
I
De-emphasis selection
Input format selection
Input format selection
Board Power
Analog R output
Analog L output
Common voltage 1/2 AVDD
Analog power supply
Analog ground
Reference voltage
Zero input Detection
I/F level selection
AK4321 (XS388A00) DAC
MAIN: IC401
PIN
NO.
I/O FUNCTION NAME
PIN
NO.
I/O FUNCTION NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDD
VSS
XSCS
XSWR
XSRD
SA0
SA1
SA2
SA3
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
VSS
VDD
FS512
FS256
FS128
VSS
FS64
XFS64
FS
VSS
XSSYNC
D8FS
D16FS
VCOBI
VCOBO
-
-
I
I
I
I
I
I
I
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
-
-
O
O
O
O
O
O
-
O
O
O
I
O
Power supply
Ground
Chip select
Light
Read
Address bus
Data bus
Ground
Power supply
Fs x 512 Bit clock output
Fs x 256 Bit clock output
Fs x 128 Bit clock output
Ground
Fs x 64 Bit clock output
Receives Fs64 clock
Sampling frequency display (Audio)
Ground
Sync signal for DSP
One eighth clock (FS)
One sixteenth clock (FS)
Input clock (PLLB)
Output clock (PLLB)
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64 VDD
VSS
PDOUTNB
PDOUTPB
XPDOB
XTALAI
XTALAO
SDINA
SDINB
XTALBI
XTALBO
UNLINB
UNLOCKB
XTALCI
XTALCO
UNLINA
UNLOCKA
VSS
VDD
RCKINA
RCKINB
VCOAI
VCOAO
PDOUTNA
PDOUTPA
XPDOA
XRST
XTCL
TEST0
TEST1
TEST2
TEST3
-
-
O
O
O
I
O
I
I
I
O
I
O
I
O
I
O
-
-
I
I
I
O
O
O
O
I
I
O
O
O
O
Power supply
Ground
PLLB phase comparison output (-)
PLLB phase comparison output (+)
PLLB out of phase
XTALA input
XTALA output
Serial data (OVR 1-4)
Serial data (OVR 5-8)
XTALCB input
XTALCB input
UNLOCKB signal input
UNLOCKB signal output
XTALC input
XTALC output
UNLOCKA signal input
UNLOCKA signal output
Ground
Power supply
External clock input A
External clock input B
Input clock (PLLA)
Output clock (PLLA)
PLLB phase comparison output (-)
PLLB phase comparison output (+)
PLLA out of phase
Reset signal
Reset signal (TEST)
Test signal output
CRVP08 (XV740A00) Gate Array
MAIN: IC119