A
B
C
D
E
G
H
I
J
K
L
CDR-1300/CDR-1300E
45
SCHEMATIC DIAGRAM (MAIN 1/2)
1
2
3
4
5
6
8
9
Point
A
Pin 74 of IC2
Point
C
VCC of IC4
and OUT of IC4
Point
B
Pin 129 of IC3
POWER ON
IC1: SN74LS06NSR
Inverter Buffer/Driver
1A
1Y
2Y
VCC
6A
1
2
3
4
11
2A
6Y
5A
12
13
14
3A
3Y
5Y
4A
5
6
7
4Y
8
9
10
GND
IC4: PST572CMT-R
System Reset
+
Vcc
Out
Gnd
1
3
2
IC7: IS41C16257-35K
DRAM
IC8: TC74HC14AF-TP1
Inverter
1A
1Y
2Y
VCC
6A
1
2
3
4
11
2A
6Y
5A
12
13
14
3A
3Y
5Y
4A
5
6
7
4Y
8
9
10
GND
IC9: TC9246F-TEL
Clock Generator
2
PD
1
REF
15
LOCK
3
VDDA
14
S2
4
AMPI
13
S1
5
AMPO
12
M2
6
VSSA
11
M1
7
XI
10
CKO
8
XO
9
VSS
16
VDD
REF
VAR
Phase
Comparator
Programable Counter
µ
-COM Interface
Lock
Detector
VCO
Selector
IC11: MBM29F800BA-70PFTN
8Mbit Flash Memory
RY/BY
Buffer
State
Control
Command
Register
Erase Voltage
Generator
Input/Output
Buffers
Chip Enable
Output Enable
Logic
Address
Latch
X-Decoder
Y-Decoder
Y-Gating
8,388,608
Cell Matrix
Timer for
Program/Erase
Program Voltage
Generator
Low Vcc Detector
VCC
RY/BY
VSS
WE
CE
OE
STB
STB
DQ0 to DQ15
BYTE
A-1
A0 to A18
RESET
Data Latch
IC202: NJM2904M
Dual OP-Amp
Q1
Q2
Q3
Q9
Q8
Q4
INPUTS
OUTPUT
V–
–
+
Q6
Q5
Q10
Q11
Q12
Q7
Q13
★
All voltage are measured with a 10M
Ω
/V DC electric volt meter.
★
Components having special characteristics are marked
s
and must be
replaced with parts having specifications equal to those originally
installed.
★
Schematic diagram is subject to change without notice.
to CD-R/W & HDD DRIVE
to CD-R/W
CLOCK
ACDR
DRAM
FLASH MEMORY
DRAM
SYSTEM
RESET
CPU
1
2
1
3
4
2
3
2
9
10
11
10
3
14
4
11
12
13
6
14
5
5
6
1
8
7
13
12
9
8
IC5: MSM5118160F-60JSR1
1Mw x 16 bit DRAM
Timing
Generator
I/O
Controller
Output
Buffers
Input
Buffers
Input
Buffers
Output
Buffers
I/O
Controller
Column Decoders
RAS
Refresh
Control Clock
14
WE
13
10
10
LCAS
31
UCAS
A0~A9
30
Vcc
21
Vss
22
Sense Amplifiers
I/O
Selector
Memory
Cells
OE
29
DQ9~DQ16
Column
Address
Buffers
Internal
Address
Counter
Row
Address
Buffers
On Chip
Vss Generator
On Chip
IVcc Generator
Row
Deco-
ders
Word
Drivers
10
10
16
16
8
8
8
8
8
8
DQ1~DQ8
8
8
age 47
TION (1)
J3
P
age 48
to OPERA
TION (7)
I7
UCAS
CAS
CLOCK
GENERATOR
CAS
RAS
OE
WE
RAS
OE
WE
LCAS
A0~A8
I/O0~I/O15
RAS
CLOCK
GENERATOR
DATA I/O BUS
REFRESH
COUNTER
COLUMN DECODERS
MEMORY ARRAY
262,144 x 16
SENSE AMPLIFIERS
WE
CONTROL
LOGICS
OE
CONTROL
LOGIC
ADDRESS
BUFFERS
R
O
W DECODER
D
A
TA I/O B
UFFERS
B
A
C
Ch 1
Ch 2
2.5
0
5.1
0.1
0
0
0
-4.9
5.1
0
2.6
2.5
2.5
0
0
0
5.1
0
0
5.1
2.5
2.6
5.1
5.1
0
2.6
0
2.5
5.1
5.1
0
2.5
2.4
5.1
1.7
1.1
5.1
0
5.1
0
5.1
2.5
0
0
0
2.6
2.5
2.5
2.6
2.5
2.5
2.5
2.6
2.6
2.6
2.6
2.6
2.6
2.6
2.6
0
0
2.6
2.6
2.6
2.6
2.6
2.6
2.6
5.1
5.1
~
~
~
~
~
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
0
~
~
~
~
2.2
~
~
2.2
2.5
5.1
~
~
~
~
~
0
~
0
5.1
0
~
5.1
0
5.1
1.3
~
~
0
0
4.9
~
0
0
2.3
2.6
5.1
0
2.6
0
0
2.5
2.8
5.1
5.1
0
~
~
~
~
~
~
~
0
~
~
5.1
2.2
2.2
2.2
2.2
2.2
2.3
2.3
0
2.2
~
~
~
2.2
~
~
~
0
2.2
5.1
4.9
4.9
5.1
5.1
0
1.4
1.3
1.6
1.8
1.8
1.9
1.9
1.6
0
2.5
2.3
2.2
5.1
5.1
1.3
5.0
5.1
0
5.1
5.1
5.1
0
5.1
5.1
0
0.8
2.5
2.5
2.4
2.7
5.1
0.2
0
5.1
5.1
5.1
5.1
0
5.1
5.1
0.2
5.1
5.1
5.1
5.1
5.1
0.2
5.1
0.2
0.2
4.8
5.1
0
0
0
5.1
5.1
1.7
1.9
1.9
1.8
5.1
1.8
1.6
1.3
1.4
4.8
1.4
2.2
2.3
2.4
2.7
5.1
5.1
0.9
2.4
2.1
0.9
0
0
1.3
1.2
1.4
2.6
3.4
3.4
2.6
2.5
1.7
2.4
2.5
2.5
0
0
1.3
1.4
1.7
2.4
3.0
2.3
1.6
3.8
4.9
5.1
2.3
0
2.5
2.5
2.6
2.5
2.7
2.4
2.3
1.7
1.4
2.4
1.3
1.6
0.9
1.3
2.1
0
5.1
2.0
1.4
1.8
5.1
1.9
1.8
1.2
1.7
4.9
1.9
2.6
0
5.1
2.2
0.9
0
5.1
0
5.1
0
0
5.1
5.1
5.1
5.1
5.1
5.0
0
5.0
4.9
5.1
0
5.1
5.1
2.6
0
5.1
5.1
5.1
0
0
0
5.1
5.1
0.9
2.4
2.1
0
0.9
5.1
0
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
5.1
0
4.9
5.1
5.0
4.9
0
0.1
5.1
~
3.8
5.1
5.0
2.3
0
2.3
5.1
0
5.1
5.1
0
2.5
5.1
2.4
0
1.6
1.9
1.9
1.8
1.8
5.1
1.6
1.3
1.4
0
2.6
1.4
1.2
1.3
2.3
2.2
0.8
0
0
0.1
2.4
2.7
2.5
2.5
2.5
2.6
2.4
1.7
1.4
1.3
1.7
3.0
2.3
1.6
5.1
2.0
0
1.4
3.4
3.4
0
4.8
w w w
.
x i a o y
u 1 6 3 .
c o m
Q Q
3 7 6 3 1 5 1 5 0
9
9
2
8
9
4
2
9
8
T E L
1 3 9 4 2 2 9 6 5 1 3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299