Yamaha CDC-E500, Руководство по обслуживанию

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2
A B C D E F G H I J
1
3
4
5
7
CDC-E500
6
38
9
2 6
7
3
8
5
1
STAND-BY
CIRCUIT
VREF
CIRCUIT
THERMAL
SHUTDOWN
CIRCUIT
VCC VS
VREF
OUT 1
OUT 2
IN 1
IN 2
GND
IC2, 3: TA8409SE
Full Bridge Motor Driver
IC5: NJM78M05FA
Voltage Regulator
V
OUT
V
IN
GND
IC200: AN8399SA-E1
CD Head Amp.
+
–
21
20
+
–
19
+
–
2
1
SUBT
AMP
+
–
GCA BCA
32
31
23
11
16
10
4 5 6 8 9 12 13 14 15
AMP GCA BCA
30
29
AMP GCA BCA 27
AMP GCA BCA
28
SUBT
NRFDET 3TENV
OFTR BDO AGC RF EQ
BAND GAP
22
25 17 7 3 26 24 18
A
C
B
D
E
F
VREF
SLPSW
GCTL
TBAL FBAL
LDRCTL
GND
VCC
CEA
RFN RF OUT RF IN CA
GC
ARF CBDO BDO COFTR OFTR
3T OUT
NRFDET
FEN
FEOUT
TEN
TE OUT
LD
PD
+
–
21
20
19
+
–
2
1
SUBT
GCA BCA
32
31
23
11
16
10
4 5 6 8 9 12 13 14 15
AMP GCA BCA
30
29
AMP GCA BCA 27
AMP GCA BCA
28
SUBT
OFTR AGC
22
25 17 7 3 26 24 18
IC207, 208: NJM2068MD
Dual OP-Amp.
– +
OUT
1
–IN
1
–V
CC
+V
CC
OUT
2
1
2
3
4 5
+IN
1
–IN
2
+IN
2
– +
6
7
8
IC300: LC75710NE
FL Display Driver
DI
SHIFT REGISTER
CG
ROM
DC
RAM
64
CL
63
CE 62
TEST
56
VFL 55
VDD 60
VSS 57
RES 61
OSCI
59
OSCO 58
CG
RAM
AD
RAM
ADDRESS
COUNTER
ADDRESS
REGISTER
GRID
CONTROL
GRID
REGISTER
AM1
AM2
AM35
G1
G2
G10
G11
AA1
AA2
AA3
AA4/G16
AA5/G15
AA6/G14
AA7/G13
AA8/G12
BRINK
GENERATOR
DUTY
GENERATOR
BLINKCYCLE
REGISTER
DISPLAY
CONTROL
DISPLAY
REGISTER
DUTYCYCLE
REGISTER
CONTROL
INSTRUCTION
DECODER
DIVIDER
TIMING
GENERATOR
OSC
1
2
35
36
37
38
39
40
41
42
43
44
45
53
54
IC1: AN4801SB-E1
4-Channel Power OP-Amp System Driver
20
5
10 11
Standby
Band gap
V
CC
/V
REF
Reset Circuit
STDY
RESET
4
PC1
3
IN1
1
IN2
V
O1-
V
O1+
8
PGND1
9
PVCC1
+ +
-
-
Direction
Detector
PV
CC/2
18
PVCC2
19
PGND2
PV
CC/2
+ -
12 13
V
O2-
V
O2+
+ +
-
-
Direction
Detector
+ -
26
IN3
14 15
V
O3-
V
O3+
+ +
-
-
Direction
Detector
+ -
25
IN4
FIN
GGND
23
SVCC
16 17
V
O4-
V
O4+
+ +
-
-
Direction
Detector
+ -
2
PC2
24 VREF
IC6 : M51953BFP
System Reset
+
–
–
7
V
CC
6 RESET
5
C
D
4
GND
R 5
µ
A
R
1.25V
IC203 : S-29190AFJA
CMOS 1kbit EEPROM
5
2
7
6
8
1
3
4
DI
Vcc
GND
DO
TEST
NC
CS
SK
Memory array Address decoder
Data register Output buffer
Mode decode logic
Clock generator
2SD1938F 1N4002S 2SB544 2SD2396 2SA933S 1SS355
MA8051-M
MA8056-M
MA8062-H
MA8062-M
MA8270-M D2SBA20 NJM2068MD
NJM78M05FA
M51953BFP
NJM2068MD
S-29190AFJA
AN4801SB-E1
TA8409SE
AN8399SA-E1 LC75710NE M30622M8A-5M4FP
1
13
14
20
21
27
28
6
7
26
1 16
17
32
33 48
49
64
1
4 8
1: OUT
2: COM
3: IN
1
9
32
16
1
17
E
C B B C
E
B
E
C
E
C
B
Anode
Cathode
–
+
~
~
Anode
Cathode
1 30
31
50
51 80
81
100
■
IC BLOCK
■
PIN CONNECTION DIAGRAM