Yamaha AO8, Руководство по обслуживанию

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*
FS Line Check
3-2. AO8-SLOT [Clock Line] Test OK
3-2. AO8-SLOT [Clock Line] Test
OK
OK
Fs 00000000
64Fs 00000000
256Fs 00000000
NG example
FS Line Check:
Now Checking …
FS Check 256Fs
3-2. AO8-SLOT [Clock Line] Test
3-2. AO8-SLOT [Clock Line] Test
NG FS Line Check:
NG SLOT4
Fs -> xx.xxx kHz
64Fs
256Fs -> xx.xxx kHzX64
-> xx.xxx kHzX256
NG SLOT6
256Fs -> xx.xxx kHzX256
(-xx.x%)
(+xx.x%)
(-xx.x%)
(-xx.x%)
NG
*
FS Line Check
Fs 00010000
64Fs 00010000
256Fs 00010100
The detected FS frequency is displayed
and the percentage deviation from the
ideal state is displayed.
The values for 64 Fs and 256 Fs are
displayed in such a way that they can be
easily grasped.
Basically, the same as up till here
*
Data Bus Test
* Voltage Check
*
Address Bus Test 00000000
00000000
OK
00000000
OK
00000000
00000000
+15V
00000000 -15V
00000000 +5V
00000000 -5V
+20V
* /CON Line Test 00000000
OK
3-1. AO8-SLOT [Initial] Test OK
3-1. AO8-SLOT [Initial] Test
OK
Data Bus Test: OK
Voltage Check: OK
/CON Line Test: OK
OK
NG example
Address Bus Test:
Now Checking …
/CON Line Test
3-1. AO8-SLOT [Initial] Test
3-1. AO8-SLOT [Initial] Test
NG Address Bus Test:
NG SLOT6 111 1111111-
NG Data Bus Test:
NG SLOT4
NG SLOT6
11111111 11111111
11111111 11111111
NG Voltage Check:
NG SLOT4
+20V => +xx.xxV
+15V => +xx.xxV
(-xx.x%)
(+xx.x%)
NG SLOT6
-5V => +xx.xxV (-xx.x%)
NG /CON Line Test: 00010100
*
Data Bus Test
* Voltage Check
*
Address Bus Test 00000100
00010100
NG
00010100
NG
00010000
00010000
+15V
00000000 -15V
00000000 +5V
00000100 -5V
+20V
* /CON Line Test 00010100
NG
NG
3-1. AO8 - Slot [Initial] Test
Checks slot operation by checking the minimum necessary number of pins. Stopped the moment an actual Addr.BusTest
or DataBusTest NG appears.
The results for each slot are displayed in order from the left. A mark is made
for each check to show the progress of the checks.
(Blank: Not yet checked; 0: Normal; 1: Abnormal; N: No response)
Displays which pin
number is NG. The main
part of the address bus is
displayed.
(1: NG; 0: OK)
First, all the voltages for one slot are
checked, then this is repeated for the
next slot. (The notation is each
voltage [x 8 slots], but the check
order is each slot [x all voltages].)
The detected voltage is displayed and the
percentage deviation from the ideal state
is displayed. This is shown for each slot. Basically, the same as up till here
3-2. AO8 - Slot [Clock Line] Test
This test checks around the slot clock.
* Digital Signal line Test
3-3. AO8-SLOT [Data Line] Test OK
3-3. AO8-SLOT [Data Line] Test
OK
OK
SI 00000000
Digital Signal Line Test:
Basically, the same as up till here
The switching of Digital Line by
the LMY-SLOT inspection jig
and ID conversion jig will be
inspected automatically.
3-3. AO8 - Slot [Data Line] Test
This test checks around the serial communications.
AO8
25
NG sample
Please refer to page 24 for NG charts.