Yamaha A5000 Editor, Руководство по обслуживанию

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A5000/A4000
10
LSI PIN DESCRIPTION
(IC507) TC203C760HF-002 (XS725A00) SWP30B (AW M Tone Generator coped with MEG) Standard W ave Processor
PIN
N O.
NAME I/O FUN CTION
PIN
N O.
NAME I/O FUN CTION
1 Vss (Gr ound) 121 VSS - (Gr ound)
2 C A0 I 122 H MD 0 I/O
3 C A1 I 123 H MD 1 I/O
4 C A2 I 124 H MD 2 I/O
5 C A3 I 125 H MD 3 I/O
6 C A4 I 126 H MD 4 I/O
7 C A5 I Address bus of inter nal register 127 H MD 5 I/O
8 C A6 I 128 H MD 6 I/O W ave memor y data bus (Upper 16 bits)
9 C A7 I 129 H MD 7 I/O
10 C A8 I 130 H MD 8 I/O
11 C A9 I 131 H MD 9 I/O
12 C A10 I 132 H MD 10 I/O
13 C A11 I 133 H MD 11 I/O
14 VSS - (Gr ound) 134 H MD 12 I/O
15 C D0 I/O 135 H MD 13 I/O
16 C D1 I/O 136 H MD 14 I/O
17 C D2 I/O 137 H MD 15 I/O
18 C D3 I/O 138 VSS - (Gr ound)
19 C D4 I/O 139 H MA0 O
20 C D5 I/O 140 H MA1 O
21 C D6 I/O 141 H MA2 O
22 C D7 I/O 142 H MA3 O
23 C D8 I/O D ata bus of internal register 143 H MA4 O
24 C D9 I/O 144 H MA5 O
25 C D10 I/O 145 H MA6 O
26 C D11 I/O 146 H MA7 O
27 C D12 I/O 147 H MA8 O
28 C D13 I/O 148 H MA9 O
29 C D14 I/O 149 H MA10 O
30 VD D - (Power supply) 150 VD D - (Power supply)
31 VSS - (Gr ound) 151 VSS - (Gr ound)
32 C D15 I/O 152 H MA11 O
33 C SN I C hip select 153 H MA12 O W ave memor y address bus
34 W R N I W rite strobe 154 H MA13 O
35 R DN I R ead strobe 155 H MA14 O
36 VD D - (Power supply) 156 H MA15 O
37 SYSH0 O 157 H MA16 O
38 SYSH1 O 158 H MA17 O
39 SYSH2 O 159 H MA18 O
40 SYSH3 O N SYS/LN SYS upper 16 bits output 160 H MA19 O
41 SYSH4 O 161 H MA20 O
42 SYSH5 O 162 H MA21 O
43 SYSH6 O 163 H MA22 O
44 SYSH7 O 164 H MA23 O
45 KON O0 O 165 H MA24 O
46 KON O1 O Key on data 166 VSS - (Gr ound)
47 KON O2 O 167 MRASN O RAS when DRAM(s ) is co nnec ted t o wav e mem ory
48 KON O3 O 168 MCASN O CAS when DRAM(s ) is co nnec ted t o wav e mem ory
49 VSS - (Gr ound) 169 MOEN O W ave memor y output enable
50 SYSL0 I/O 170 MW EN O W ave memor y write enable
51 SYSL1 I/O 171 VSS - (Gr ound)
52 SYSL2 I/O 172 LMD0 I/O
53 SYSL3 I/O N SYS input/LN SYS output lower 8 bits 173 LMD1 I/O
54 SYSL4 I/O 174 LMD2 I/O
55 SYSL5 I/O 175 LMD3 I/O
56 SYSL6 I/O 176 LMD4 I/O
57 SYSL7 I/O 177 LMD5 I/O
58 KON I0 I 178 LMD6 I/O
59 KON I1 I Key on data input 179 LMD7 I/O W ave memor y data bus (Low er 16 bits)
60 VD D - (Power supply) 180 VD D - (Power supply)
61 VSS - (Gr ound) 181 VSS - (Gr ound)
62 KON I2 I 182 LMD8 I/O
63 KON I3 I 183 LMD9 I/O
64 D AC0 O D AC output 184 LMD10 I/O
65 D AC1 O 185 LMD11 I/O
66 W C LK O D AC0/D AC1 word clock 186 LMD12 I/O
67 MELO 0 O 187 LMD13 I/O
68 MELO 1 O 188 LMD14 I/O
69 MELO 2 O 189 LMD15 I/O
70 MELO 3 O MEL wave data output 190 VSS - (Gr ound)
71 MELO 4 O 191 LMA0 O
72 MELO 5 O 192 LMA1 O
73 MELO 6 O 193 LMA2 O
74 MELO 7 O 194 LMA3 O
75 VD D - (Power supply) 195 LMA4 O
76 AD LR O AD C word clock 196 LMA5 O
77 MELI0 I 197 LMA6 O
78 MELI1 I 198 LMA7 O
79 MELI2 I 199 LMA8 O
80 MELI3 I MEL wave data input 200 LMA9 O
81 MELI4 I 201 LMA10 O
82 MELI5 I 202 LMA11 O
83 MELI6 I 203 VSS - (Gr ound)
84 MELI7 I 204 LMA12 O
85 VSS - (Gr ound) 205 LMA13 O W ave memor y address bus (Lower data memory)
86 R CASN O D RAM column address strobe (RAS signal) 206 LMA14 O
87 R A8 O 207 LMA15 O
88 R A7 O 208 LMA16 O
89 R A6 O 209 LMA17 O
90 VD D - (Power supply) 210 VD D - (Power supply)
91 VSS - (Gr ound) 211 VSS - (Gr ound)
92 R A5 O D RAM address bus 212 LMA18 O
93 R A4 O 213 LMA19 O
94 R A3 O 214 LMA20 O
95 R A2 O 215 LMA21 O
96 R A1 O 216 LMA22 O
97 R A0 O 217 LMA23 O
98 R RASN O D RAM row address strobe (R AS signal) 218 LMA24 O
99 R W EN O D ARM w rite enable 219 VSS - (Gr ound)
100 VSS - (Gr ound) 220 SYO O Sync. signal for master clock
101 R D7 I/O 221 SYOD O Sync. signal for H CLK/Q CLK
102 R D6 I/O 222 QC LK O 1/12 master clock (64F s)
103 R D5 I/O 223 H CLK O 1/6 master clock (128F s)
104 R D4 I/O 224 C K256 O 1/3 master clock (256F s)
105 R D3 I/O 225 SYSCLK O 1/2 master clock (384F s)
106 R D2 I/O 226 VD D - (Power supply)
107 R D1 I/O 227 SYI I Sync. clock
108 R D0 I/O 228 MCLKI I Master clock input
109 VSS - (Gr ound) 229 MCLKO O Master clock output
110 R D17 I/O 230 VD D - (Power supply)
111 R D16 I/O D RAM data bus 231 XIN I C rystal osc. input
112 R D15 I/O 232 XOU T O C rystal osc. output
113 R D14 I/O 233 VSS - (Gr ound)
114 R D13 I/O 234 IC N I Initial clear
115 R D12 I/O 235 C HIP2 I 2 chips mode enable
116 R D11 I/O 236 SLAVE I Master/Slave select when 2 chips mode
117 R D10 I/O 237 TEST ON I
118 R D9 I/O 238 AC IN I Test pin
119 R D8 I/O 239 D CT EST I
120 VD D - (Power supply) 240 VD D - (Power supply)