Yaesu Mark-V FT-1000MP, Техническое дополнение

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Circuit Description
4-6
via Q8044 (
2SC2714Y
) and T8017/T8016. Like the main PLL
circuit, the PLL circuit is a frequency mixing type composed mainly
of a VCO, mixer, PLL IC, and loop filter.
The VCO consists of four circuits (VCO1 through VCO4). The
47.31 ~ 77.21 MHz oscillation frequency range is divided into
four bands, which are allocated to the four VCO circuits.
VCO1 to VCO4 are composed of oscillator FETs Q8034 ,
Q8047 , Q8051 , and Q8058 (all
2SK210BL
), variable-capacity
diodes D8021 , D8024 , D8027 , and D8031 (all
HVU306A
), and
oscillator coils L8007, L8010, L8020, L8024. The VCO switch-
ing signal from connector J8003 drives switching transistors Q8040,
Q8050 , Q8056 , and Q8063 (all 2SC4047 ) to switch the source
line of each oscillator FET.
The oscillation signal (47.31 ~ 77.21 MHz) from the VCO is
fed to mixer Q8043 ( µPC1037H ) through buffer amplifier FET
Q8041 (
2SK210GR
) and buffer amplifier transistor Q8042
(
2SC2714Y
).
The reference oscillator signal (10.48576 MHz) from the LO-
CAL Unit that has been amplified by Q8066 and Q8060 (both
2SC2812 ) and divided into 5.24288 MHz signals by Q8054
(
TC74HC74AF
) is fed to mixer Q8055 (SN16913) through a LPF
composed of C8152, C8153, C8164, C8165, C8166, L8012, and
L8013.
At the same time, the 286.28 ~ 364.20 kHz output from the
RX2 PLL-DDS Unit is fed to mixer Q8055 to obtain a 5.52516 ~
5.60708 MHz signal.
This signal passes through ceramic filter CF8004
( SFT5.57MA ) and is fed to mixer Q8038 ( SN16913 ), together
with the 46.755 MHz output of the 2nd L.O. that has been buffer-
amplified by
Q8045 ( 2SC2714Y ), to produce a 41.14792 ~
41.22984 MHz signal. This is then passed through a BPF com-
posed of T8013, T8014, and C8087, is amplified by
Q8037
(
2SC2714Y
), and then is fed to mixer Q8043 via T8012.
The output of mixer Q8043 ranges from 6.1440 ~ 36.0488
MHz, and passes through a 9th-order Chebyshev LPF which is
composed of coils L8015-L8019 and capacitors C8157-C1861 plus
C8168-C8173. This is passed to PLL IC
Q8061 ( MB87086AFP )
after it is amplified by FET Q8053 (
2SK210GR
) and transistor
Q8052 ( 2SC2714Y ).
At the same time, the 10.48576 MHz reference oscillator sig-
nal from the LOCAL Unit is also passed to PLL IC Q8061 via
buffer amplifier Q8064 after amplification by Q8065 (both
2SC2812
).
The phase difference is compared between the reference fre-
quency and the frequency of the signal input to the PLL IC, and a
pulse corresponding to the phase difference is developed to con-
trol the VCO frequency by a loop filter consisting of an active
filter at FET
Q8059 (
2SK208Y
), transistor Q8062 (
2SC2714Y
),
and a secondary lag filter composed of a resistor and capacitor.
The controlled VCO output is amplified by Q8035
(
2SC2714Y
) and Q8036 (
2SC2053
) and passes through a LPF
composed of coils L8005/L8006 and capacitors C8098, C8099,
and C8104-8106. It is then fed to the 1st mixer circuit through an
attenuator.
DSP Circuit
The DSP circuit consists mainly of DSP (Digital Signal Pro-
cessor) IC Q7101 ( µPD77016GM ), a AD/DA converter IC, and
filter circuit. The functions performed by this circuit are SSB and
AM demodulation, auto-notch, noise reduction, audio filtering, etc.
in the receiving system and SSB generation/modulation and audio
equalizing on the transmit side.
Analog-Digital Converter Circuit
(Transmission System)
The audio signal from the microphone that has passed through
electronic volume control Q3044 (
M51131L
) in the AF Unit is
fed to the DSP-A Unit through connectors J3037/J7001. It then
passes through a 5th-order active HPF (cut-off frequency = 80 Hz)
composed of op-amp ICs
Q7004-1 / Q7004-2 ( µPC457G2 ),
R7001-7004, R7007, and C7001, C7002, C7004-7006 to elimi-
nate unwanted frequency components below the cut-off frequency.
The signal then passes through a inverting/non-inverting buffer
amplifier circuit composed of op-amp ICs Q7005-2 to Q7005-4
( NJM3403AM ) prior to input to A/D converter IC Q7001
(
AK4501
), where it is converted into a 16-bit digital signal. As
16-bit serial data, this signal is transmitted to DSP IC Q7101 on
the DSP-D Unit via connector J7003.
Digital-Analog Converter Circuit
(Transmission System)
The serial digital data input to the D/A converter IC Q7001 is
converted into an analog signal and passed through a differential
amplification type tertiary LPF (cut-off frequency fc = 18 kHz)
composed of op-amp ICs
Q7007-1 / Q7007-2 ( µPC457G2 ),
R7037-R7043, and C7043-C7046 to suppress out-of-band energy,
random noise, etc. The signal is then fed to the AF Unit as an audio
signal or SSB signal of 10.24 kHz (suppressed carrier) via con-
nector J7001.
Digital Signal Processor Circuit (Transmission System)
In the transmission system, this circuit has a microphone equal-
izing function and digital modulator function. The A/D-converted
signal data is subjected to tone quality processing and is fed to the
digital modulator. When desired, it is possible to disable micro-
phone equalization and digital modulation. The serial audio data
or SSB data processed by the DSP IC is fed to the D/A converter
in the DSP-A Unit via connector J7103.
The signal from the DSP Unit is fed to balanced modulator IC
Q3048 . When the DSP-enabled SSB modulation function is used,
the balanced modulator IC operates as a double balanced mixer (fre-
quency mixer). In this case, a carrier (local) signal (LSB = 466.74
kHz, USB = 463.74 kHz) generated by the DDS-CAR Unit and SSB
signal of 10.24 kHz suppressed carrier apply a mixed differential