Yaesu FT-817 -, Техническое дополнение

Страница: 12 / 111

12
Circuit Description
stant ALC amplifier, and a transmit signal control circuit
on the MAIN Unit.
The forward voltage from connector J1003 on the MAIN
Unit is added with a DC control voltage and is then ap-
plied to op-amp IC
Q1097 (
NJM2902V
).
The reflected voltage is added with a DC control voltage
and is then applied to op-amp IC
Q1098 (
NJM2904V
), In
the event of high SWR conditions (SWR of 3:1 or more),
transmitter output is reduced and a "High SWR" warning
appears, thus protecting the PA Unit from potential dam-
age and alerting the operator to the high SWR situation.
The ALC amplifier amplifies the "forward" DC output via
transistor
Q1019 (
2SC4154
). This output then passes
through a fast-attack, slow-delay RC time-constant cir-
cuit which consists of R1097 and C1113 for the input to
the Tx signal control circuit on the MAIN Unit.
The TX control circuit adjusts the IF amplifier gain via
gate 2 of FET
Q1007 (
BB304CDW
) of the 68.33 MHz IF
amplifier circuit to prevent the power output from exceed-
ing the preset level.
PLL Frequency Synthesizer
The PLL Frequency Synthesizer consists mainly of a mas-
ter reference oscillator circuit, 2nd local oscillator circuit,
plus the PLL IC, CAR-DDS, and REF-DDS units, which
digitally synthesize carrier outputs, and a PLL circuit
which contains a voltage controlled oscillator (VCO).
Master Reference Oscillator Circuit
The master reference oscillator uses a crystal oscillator
(oscillation frequency: 22.625MHz) composed of
Q5001
(
2SC4400
), X5001, TC5001, C5001, R5005, and associated
components. The reference oscillator signal passes
through buffer amplifier
Q5002 (
2SC4400
), C5004, C5007,
R5003, R5004, R5007, and is then fed to the MAIN Unit
via J5002.
CAR-DDS Circuit /REF-DDS Circuit
DDS ICs Q1031 (
AD9835BRU
) and Q2016 (
AD9850BRS
)
each contain a shift register, selector, phase accumulator,
and ROM.
The reference oscillation frequency (22.625MHz) that is
delivered to each of the DDS Units is applied to each DDS
IC after amplification by transistors
Q1028 / Q2020 (both
2SC4400
).
The DDS outputs contain digital amplitude data corre-
sponding to serial frequency data from CPU IC
Q4004
(
HD6432345
) of the PANEL Unit. The DDS frequency
range is 453.5 ~ 466.5 kHz (cf = 455.0 kHz) for the CAR-
DDS, and 7.2-8.0 MHz for the REF DDS.
2nd Local Oscillator Circuit
The 2nd L.O. circuit is a Hartley-type overtone oscillator
circuit (frequency: 67.875 MHz) composed of
Q1047
(
2SC4400
) on the MAIN Unit.
1st Local Oscillator Circuit
VCO output is buffer-amplified by Q2008 (
2SC4400
),
Q2011 , Q2014 , and Q2016 (all
2SC5374
) and passes
through a low-pass filter. It is then fed to the Tx/Rx fre-
quency mixer circuitry on the MAIN Unit.
PLL Circuit
The PLL circuit is a frequency mixing type composed of a
VCO, mixer, PLL IC, and loop filter.
The VCO consists of five circuits (VCO1, VCO2, VCO3,
VCO4, and VCO5), with a frequency range of 68.430-
538.330 MHz divided into five bands, allocated to the five
VCO circuits. VCO1-VCO5 consist mainly of FETs
Q2004 ,
Q2005 , and Q2006 (all
2SK210GR
), transistors Q2009 ,
Q2010 (both
2SC5374
), diodes D2001 - D2006 (all
HVC362
), D2007 (
1SV282
), D2008 (
1SV281
), and D2009
(
1SV286
), and coils T2001-T2003, L2010, and L2011.
The VCO switching signal from connector J2002 is used
to drive switching transistors
Q2001 , Q2002 , Q2003 ,
Q2012 , and Q2013 (all
DTC124EU
) to switch the source
terminal of the oscillator FET.
The 68.430-538.330 MHz VCO signal is fed to mixer D1047
(
GN2011-Q
).
The REF-DDS signal (7.2-8.0 MHz) is fed to PLL IC Q2022
(
UPC2713T
: Lot 1 - 74,
UPC2710
: Lot 75 -) after it passes
through a LPF composed of C2064, C2067, C2069, C2071,
C2075, L2014, L2015, and L2016 , and buffer amplifier
Q2019 (
2SC4400
).
The phase of the reference frequency and that of the sig-
nal input to PLL IC are compared, and a signal whose
pulse corresponds to the phase difference is produced.
The VCO frequency is controlled by a first lag filter which
consists of R2057, R2065, R2062, and C2090 and a second-
ary lag filter composed of C2085, C2088, and R2053.