Xycom CHIP4e+, Руководство пользователя

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Manual
20
Offset Registers
The following registers are located starting at the I/O location defined by register
234h, bits 6 and 7.
Table 0-10. I/O Port Selection (Port Address)
I/O Port Selection Port Address
00 180h
01 2E0h
10 3E0h
11 300h
Offset 0 Page Register for Programming (Port Address)
Offset 0 is a read-only register that checks the battery status.
Table 0-11. Offset 0 Page Register for Programming (Port Address)
Bit Signal Result R/W
0 Battery status 0 = Battery good
1 = Battery failed R
1-7 Reserved 0 R
Offset 1 Page Register for Programming (Port A1)
Offset 1 controls the SRAM paging bits.
Table 0-12. Offset 1 Page Register for Programming (Port A1)
Bit Signal Result R/W
0 Control RAM15 ROM address 15 - page control bit R/W
1 Control RAM16 ROM address 16 - page control bit R/W
2 Control RAM17 ROM address 17 - page control bit R/W
3 Reserved 0 R
4 Reserved 0 R
5 Reserved R/W
6 Reserved 0 R
7 Reserved 0 R