XOCECO LC27U7D, Руководство по обслуживанию

Страница: 19 / 70

17
Pin Name Pin Type Function Pin
LVA2M Output A-Link Negative LVDS Differential Data Output 167
LVA2P Output A-Link Positive LVDS Differential Data Output 166
LVA3M Output A-Link Negative LVDS Differential Data Output 161
LVA3P Output A-Link Positive LVDS Differential Data Output 160
LVACKM Output A-Link Negative LVDS Differential Data Output 165
LVACKP Output A-Link Positive LVDS Differential Data Output 164
LVB0M Output B-Link Negative LVDS Differential Data Output 187
LVB0P Output B-Link Positive LVDS Differential Data Output 186
LVB1M Output B-Link Negative LVDS Differential Data Output 181
LVB1P Output B-Link Positive LVDS Differential Data Output 180
LVB2M Output B-Link Negative LVDS Differential Data Output 179
LVB2P Output B-Link Positive LVDS Differential Data Output 178
LVB3M Output B-Link Negative LVDS Differential Data Output 175
LVB3P Output B-Link Positive LVDS Differential Data Output 174
LVBCKM Output B-Link Negative LVDS Differential Data Output 177
LVBCKP Output B-Link Positive LVDS Differential Data Output 176
GPO Interface
Pin Name Pin Type Function Pin
PWM0 Output GPO with PWM Function; 4mA driving strength 200
PWM1 Output GPO with PWM Function; 4mA driving strength 201
GPO[1] I/O GPO / FIELD input; 4mA driving strength 78
GPO[2] I/O GPO / Digital VSYNC Input; 4mA driving strength 77
GPO[3] I/O GPO / DE Input; 4mA driving strength 76
GPO[4] I/O GPO / Secondary Video Clock Input; 4mA driving
strength 52
GPO[5] I/O GPO / Digital HSYNC Input; 4mA driving strength 51
DRAM Interface
Pin Name Pin Type Function Pin
MVREF Input Reference Voltage for DDR SDRAM
Interface 104
MCLKE Output DRAM Memory Clock Enable 105
MCLKZ Output DRAM Memory clock Complementary /Input 106