USB Audio 2.0 Reference Design, XS1-L1 Edition Hardware Manual (1.0)
4/18
2
XS1-L1 Device [A]
The board is based on a single XS1-L1 device in a 128 pin TQFP package.
The XS1-L1 consists of a single XCore, which comprises an event-driven multi-
threaded processor with tightly integrated general purpose I/O pins and 64 KBytes
of on-chip RAM and 8 KBytes of OTP (One Time Programmable) memory.
The processor has time-aware ports that are directly connected to the I/O pins.
Examples of how to write software that interfaces over these ports is provided in
Programming XC on XMOS Devices
.
2.1
Clocking
A discrete 13MHz oscillator is used to feed the XS1-L1 reference clock input and
also the USB3318 USB transceiver. The L1 has the MODE1 and MODE0 pins wired
to ground which sets the internal XS1-L1 PLL multiplication factor to 30.75. This
results in a core clock frequency of 399.75MHz and an I/O reference clock frequency
of 99.9375MHz.
2.2
Reset
A supply voltage supervisor connected to the 1V0 core supply is used to provide a
reset to the L1. This ensures the device will be reset at power on and also provides
predictable behaviour under brownout conditions. The device can also be reset over
the XSYS debug interface.
2.3
Boot
The boot mode of the device is set by the MODE3 and MODE2 pins which are
connected together on the board. With MODE3 and MODE2 both high (default), the
device will boot from the 1Mb SPI FLASH on the board. With MODE3 and MODE2 both
low, the device will not boot from SPI FLASH allowing boot instead via JTAG over the
XSYS debug link.
Without anything connected to the XSYS interface, the board will boot from SPI FLASH.
With the XTAG2 connected to the XSYS interface, the host can control the boot mode
of the device by way of the TRST_N line.
www.xmos.com
electronic components distributor
