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March 30, 1998 (Version 1.5)

4-23

XC4000XL 5-Volt Tolerant I/Os

The I/Os on the XC4000XL are fully 5-volt tolerant even
though the V

is 3.3 volts. This allows 5 V signals to

directly connect to the XC4000XL inputs without damage,
as shown in

Table 9

. In addition, the 3.3 volt V

can be

applied before or after 5 volt signals are applied to the I/Os.
This makes the XC4000XL immune to power supply
sequencing problems.

Registered Inputs

The I1 and I2 signals that exit the block can each carry
either the direct or registered input signal.

The input and output storage elements in each IOB have a
common clock enable input, which, through configuration,
can be activated individually for the input or output flip-flop,
or both. This clock enable operates exactly like the EC pin
on the XC4000 Series CLB. It cannot be inverted within the
IOB.

The storage element behavior is shown in

Table 10

Table 10: Input Register Functionality
(active rising edge is shown)

Optional Delay Guarantees Zero Hold Time

The data input to the register can optionally be delayed by
several nanoseconds. With the delay enabled, the setup
time of the input flip-flop is increased so that normal clock
routing does not result in a positive hold-time requirement.
A positive hold time requirement can lead to unreliable,
temperature- or processing-dependent operation.

The input flip-flop setup time is defined between the data
measured at the device I/O pin and the clock input at the
IOB (not at the clock pin). Any routing delay from the device
clock pin to the clock input of the IOB must, therefore, be
subtracted from this setup time to arrive at the real setup
time requirement relative to the device pins. A short speci-
fied setup time might, therefore, result in a negative setup
time at the device pins, i.e., a positive hold-time require-
ment.

When a delay is inserted on the data line, more clock delay
can be tolerated without causing a positive hold-time
requirement. Sufficient delay eliminates the possibility of a
data hold-time requirement at the external pin. The maxi-
mum delay is therefore inserted as the default.

The XC4000E IOB has a one-tap delay element: either the
delay is inserted (default), or it is not. The delay guarantees
a zero hold time with respect to clocks routed through any
of the XC4000E global clock buffers. (See

“Global Nets and

Buffers (XC4000E only)” on page 4-36

for a description of

the global clock buffers in the XC4000E.) For a shorter
input register setup time, with non-zero hold, attach a
NODELAY attribute or property to the flip-flop.

The XC4000X IOB has a two-tap delay element, with
choices of a full delay, a partial delay, or no delay. The
attributes or properties used to select the desired delay are
shown in

Table 11

. The choices are no added attribute,

MEDDELAY, and NODELAY. The default setting, with no
added attribute, ensures no hold time with respect to any of
the XC4000X clock buffers, including the Global Low-Skew
buffers. MEDDELAY ensures no hold time with respect to
the Global Early buffers. Inputs with NODELAY may have a
positive hold time with respect to all clock buffers. For a
description of each of these buffers, see

“Global Nets and

Buffers (XC4000X only)” on page 4-38

Table 11: XC4000X IOB Input Delay Element

Table 9: Supported Sources for XC4000 Series Device
Inputs

Source

XC4000E/EX

Series Inputs

XC4000XL

Series Inputs

5 V,

TTL

5 V,