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Xilinx XC4000E Series, Руководство пользователя

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March 30, 1998 (Version 1.5)

4-11

Set/Reset

An asynchronous storage element input (SR) can be con-
figured as either set or reset. This configuration option
determines the state in which each flip-flop becomes oper-
ational after configuration. It also determines the effect of a
Global Set/Reset pulse during normal operation, and the
effect of a pulse on the SR pin of the CLB. All three set/
reset functions for any single flip-flop are controlled by the
same configuration data bit.

The set/reset state can be independently specified for each
flip-flop. This input can also be independently disabled for
either flip-flop.

The set/reset state is specified by using the INIT attribute,
or by placing the appropriate set or reset flip-flop library
symbol.

SR is active High. It is not invertible within the CLB.

Global Set/Reset

A separate Global Set/Reset line (not shown in

Figure 2

)

sets or clears each storage element during power-up,
reconfiguration, or when a dedicated Reset net is driven
active. This global net (GSR) does not compete with other
routing resources; it uses a dedicated distribution network.

Each flip-flop is configured as either globally set or reset in
the same way that the local set/reset (SR) is specified.
Therefore, if a flip-flop is set by SR, it is also set by GSR.
Similarly, a reset flip-flop is reset by both SR and GSR.

GSR can be driven from any user-programmable pin as a
global reset input. To use this global net, place an input pad
and input buffer in the schematic or HDL code, driving the
GSR pin of the STARTUP symbol. (See

Figure 3

.) A spe-

cific pin location can be assigned to this input using a LOC
attribute or property, just as with any other user-program-
mable pad. An inverter can optionally be inserted after the
input buffer to invert the sense of the Global Set/Reset sig-
nal.

Alternatively, GSR can be driven from any internal node.

Data Inputs and Outputs

The source of a storage element data input is programma-
ble. It is driven by any of the functions F’, G’, and H’, or by
the Direct In (DIN) block input. The flip-flops or latches
drive the XQ and YQ CLB outputs.

Two fast feed-through paths are available, as shown in

Figure 2

. A two-to-one multiplexer on each of the XQ and

YQ outputs selects between a storage element output and
any of the control inputs. This bypass is sometimes used by
the automated router to repower internal signals.

Control Signals

Multiplexers in the CLB map the four control inputs (C1 - C4
in

Figure 2

) into the four internal control signals (H1, DIN/

H2, SR/H0, and EC). Any of these inputs can drive any of
the four internal control signals.

When the logic function is enabled, the four inputs are:

•

EC — Enable Clock

•

SR/H0 — Asynchronous Set/Reset or H function
generator Input 0

•

DIN/H2 — Direct In or H function generator Input 2

•

H1 — H function generator Input 1.

When the memory function is enabled, the four inputs are:

•

EC — Enable Clock

•

WE — Write Enable

•

D0 — Data Input to F and/or G function generator

•

D1 — Data input to G function generator (16x1 and
16x2 modes) or 5th Address bit (32x1 mode).

Using FPGA Flip-Flops and Latches

The abundance of flip-flops in the XC4000 Series invites
pipelined designs. This is a powerful way of increasing per-
formance by breaking the function into smaller subfunc-
tions and executing them in parallel, passing on the results
through pipeline flip-flops. This method should be seriously
considered wherever throughput is more important than
latency.

To include a CLB flip-flop, place the appropriate library
symbol. For example, FDCE is a D-type flip-flop with clock
enable and asynchronous clear. The corresponding latch
symbol (for the XC4000X only) is called LDCE.

In XC4000 Series devices, the flip flops can be used as
registers or shift registers without blocking the function
generators from performing a different, perhaps unrelated
task. This ability increases the functional capacity of the
devices.

The CLB setup time is specified between the function gen-
erator inputs and the clock input K. Therefore, the specified
CLB flip-flop setup time includes the delay through the
function generator.

Using Function Generators as RAM

Optional modes for each CLB make the memory look-up
tables in the F’ and G’ function generators usable as an
array of Read/Write memory cells. Available modes are
level-sensitive (similar to the XC4000/A/H families), edge-
triggered, and dual-port edge-triggered. Depending on the

PAD

IBUF

GSR
GTS

CLK DONEIN

Q1Q4

Q2
Q3

STARTUP

X5260

Figure 3:   Schematic Symbols for Global Set/Reset

Содержание XC4000E Series

Страница 1: ...Control Signals 4 11 Using FPGA Flip Flops and Latches 4 11 Using Function Generators as RAM 4 11 Fast Carry Logic 4 18 Input Output Blocks IOBs 4 21 IOB Input Signals 4 21 IOB Output Signals 4 24 Ot...

Страница 2: ...55 Configuration Through the Boundary Scan Pins 4 55 Readback 4 56 Readback Options 4 57 Read Capture 4 57 Read Abort 4 57 Clock Select 4 57 Violating the Maximum High and Low Time Specification for t...

Страница 3: ...ts 4 92 XC4000EX Pin to Pin Input Parameter Guidelines 4 93 XC4000EX Global Early Clock Set Up and Hold for IFF 4 93 XC4000EX Global Early Clock Set Up and Hold for FCL 4 93 XC4000EX Input Threshold A...

Страница 4: ...Pin Locations for XC4025E XC4028EX XL Devices 4 125 Pin Locations for XC4036EX XL 4 128 Pin Locations for XC4044XL Devices 4 131 Pin Locations for XC4052XL Devices 4 135 Pin Locations for XC4062XL De...

Страница 5: ...imization Low Voltage Versions Available Low Voltage Devices Function at 3 0 3 6 Volts XC4000XL High Performance Low Voltage Versions of XC4000EX devices Additional XC4000X Series Features Highest Per...

Страница 6: ...programmed devices Taking Advantage of Reconfiguration FPGA devices can be reconfigured to change logic function while resident in the system This capability gives the sys tem designer a new degree o...

Страница 7: ...carry chain through a single CLB TBYP have improved by as much as 50 from XC4000 values See Fast Carry Logic on page 4 18 for more information Select RAM Memory Edge Triggered Synchronous RAM Modes Th...

Страница 8: ...in XC4000X Only Increased Routing New interconnect in the XC4000X includes twenty two additional vertical lines in each column of CLBs and twelve new horizontal lines in each row of CLBs The twelve Q...

Страница 9: ...e function generator outputs However the stor age elements and function generators can also be used independently These storage elements can be configured as flip flops in both XC4000E and XC4000X dev...

Страница 10: ...ible for each storage element Any inverter placed on the clock input is automatically absorbed into the CLB Clock Enable The clock enable signal EC is active High The EC pin is shared by both storage...

Страница 11: ...own in Figure 2 A two to one multiplexer on each of the XQ and YQ outputs selects between a storage element output and any of the control inputs This bypass is sometimes used by the automated router t...

Страница 12: ...s Edge Triggered Synchronous data written by the designated edge of the CLB clock WE acts as a true clock enable Level Sensitive Asynchronous an external WE signal acts as the write strobe The selecte...

Страница 13: ...ps between CLB pins and RAM inputs and outputs for single port edge triggered mode are shown in Table 6 The Write Clock input WCLK can be configured as active on either the rising edge default or the...

Страница 14: ...ITE PULSE LATCH ENABLE LATCH ENABLE K CLOCK WE D1 D0 EC WRITE PULSE MUX 4 4 Figure 5 16x2 or 16x1 Edge Triggered Single Port RAM G 4 G1 G4 F1 F4 C1 C4 WRITE DECODER 1 of 16 DIN 16 LATCH ARRAY X6754 4...

Страница 15: ...ive Timing Mode Note Edge triggered mode is recommended for all new designs Level sensitive mode also called asynchronous mode is still supported for XC4000 Series backward com patibility with the XC4...

Страница 16: ...contents are defined via an INIT attribute or property attached to the RAM or ROM symbol as described in the schematic library guide If not defined all RAM contents are initialized to all zeros by def...

Страница 17: ...ED AH T X6462 Figure 9 Level Sensitive RAM Write Timing Enable G 4 G1 G4 F1 F4 WRITE DECODER 1 of 16 DIN 16 LATCH ARRAY X6746 4 READ ADDRESS MUX Enable F WRITE DECODER 1 of 16 DIN 16 LATCH ARRAY 4 REA...

Страница 18: ...hain in XC4000E devices can run either up or down At the top and bottom of the columns where there are no CLBs above or below the carry is propagated to the right See Figure 12 In order to improve spe...

Страница 19: ...4000X devices when the minor logic changes are taken into account The fast carry logic can be accessed by placing special library symbols or by using Xilinx Relationally Placed Mac ros RPMs that alrea...

Страница 20: ...1998 Version 1 5 D Q S R EC YQ Y DIN H G F G H D Q S R EC XQ DIN H G F H X H F G G4 G3 G2 G1 F F3 F2 F1 F4 F CARRY G CARRY C C DOWN CARRY LOGIC D C C UP K S R EC H1 X6699 OUT IN OUT IN IN COUT0 Figur...

Страница 21: ...iggered flip flop or a level sensitive latch The choice is made by placing the appropriate library sym bol For example IFD is the basic input flip flop rising edge triggered and ILD is the basic input...

Страница 22: ...Buffer Passive Pull Up Pull Down 2 I1 X6704 Figure 16 Simplified Block Diagram of XC4000E IOB Q Flip Flop Latch Fast Capture Latch D Q Latch D G D 0 1 CE CE Q Out T Output Clock I Input Clock Clock E...

Страница 23: ...e hold time requirement Sufficient delay eliminates the possibility of a data hold time requirement at the external pin The maxi mum delay is therefore inserted as the default The XC4000E IOB has a on...

Страница 24: ...al Early buffer and clocks the Fast Capture latch appropriately Figure 17 on page 4 22 also shows a two tap delay on the input By default if the Fast Capture latch is used the Xilinx software assumes...

Страница 25: ...de and more than 5 ns dura tion This level of ground bounce may cause undesired transient behavior on an output or in the internal logic This restriction is common to all high speed digital ICs and is...

Страница 26: ...se sensitivity The configurable pull up resistor is a p channel transistor that pulls to Vcc The configurable pull down resistor is an n channel transis tor that pulls to Ground The value of these res...

Страница 27: ...8 Three State Buffer Modes The 3 state buffers can be configured in three modes Standard 3 state buffer Wired AND with input on the I pin Wired OR AND Standard 3 State Buffer All three pins are used P...

Страница 28: ...ey can be combined with other logic to form a PAL like AND OR struc ture The decoder outputs can also be routed directly to the chip outputs For fastest speed the output should be on the same chip edg...

Страница 29: ...cks Global routing consists of dedicated networks primarily designed to distribute clocks throughout the device with minimum delay and skew Global routing can also be used for other high fanout signal...

Страница 30: ...length lines associated with each CLB These lines connect the switch ing matrices that are located in every row and a column of CLBs Single length lines are connected by way of the program mable switc...

Страница 31: ...G LE D O U BLE LO N G G LO BAL QUAD LONG SINGLE DOUBLE LONG LO N G DOUBLE D O U BLE Q U AD G LO BAL Common to XC4000E and XC4000X XC4000X only Programmable Switch Matrix CLB D IR EC T FEED BAC K DIREC...

Страница 32: ...ndent inputs and up to two independent outputs Only one of the inde pendent inputs can be buffered The place and route software automatically uses the timing requirements of the design to determine wh...

Страница 33: ...terconnect delays I O Routing XC4000 Series devices have additional routing around the IOB ring This routing is called a VersaRing The VersaRing facilitates pin swapping and redesign without affecting...

Страница 34: ...l Quad Single Double Long Direct Connect Long INTERCONNECT IOB WED WED WED IOB Figure 32 High Level Routing Diagram of XC4000 Series VersaRing Left Edge WED Wide Edge Decoder IOB I O Block shaded arro...

Страница 35: ...C T A L E D G E D E C O D E QUAD LONG SINGLE DOUBLE LONG L O N G DOUBLE D O U B L E G L O B A L IK OK I1 CE I2 T O DECODER DECODER Common to XC4000E and XC4000X XC4000X only IOB IOB DIRECT Figure 34...

Страница 36: ...y Global buffers offer the shortest delay and negligible skew Four Secondary Global buffers have slightly longer delay and slightly more skew due to poten tially heavier loading but offer greater flex...

Страница 37: ...n X4 4 IOB CLOCKS CLB CLOCKS PER COLUMN CLB CLOCKS PER COLUMN CLB CLOCKS PER COLUMN CLB CLOCKS PER COLUMN locals locals locals locals locals BUFGLS locals BUFGLS BUFGLS BUFGLS BUFGLS BUFGE BUFGE BUFGE...

Страница 38: ...pe in parallel This configuration is particu larly useful when using the Fast Capture latches as described in IOB Input Signals on page 4 21 Paired Glo bal Early and Global Low Skew buffers share a co...

Страница 39: ...g expla nation Each Global Early buffer can access the eight vertical Glo bal lines for all CLBs in the quadrant Therefore only one fourth of the CLB clock pins can be accessed This restric tion is in...

Страница 40: ...onditions may be capable of driving sinking up to 10 times as much current under best case conditions Noise can be reduced by minimizing external load capaci tance and reducing simultaneous output tra...

Страница 41: ...o Vcc User I O Pins That Can Have Special Functions RDY BUSY O I O During Peripheral mode configuration this pin indicates when it is appropriate to write another byte of data into the FPGA The same s...

Страница 42: ...l global net with short delay and minimal skew If not used to drive a global buffer any of these pins is a user pro grammable I O The PGCK1 PGCK4 pins drive the four Primary Global Buffers Any input p...

Страница 43: ...nfiguration DIN is a user programmable I O pin DOUT O I O During configuration in any mode but Express mode DOUT is the serial configuration data output that can drive the DIN of daisy chained slave F...

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